baseline.asc

Version 4
SHEET 1 9124 2520
WIRE -1392 -1648 -1392 -1664
WIRE -1392 -1552 -1392 -1568
WIRE 768 -1392 624 -1392
WIRE 624 -1360 624 -1392
WIRE 304 -1280 96 -1280
WIRE 576 -1280 304 -1280
WIRE 624 -1232 624 -1264
WIRE 624 -1232 384 -1232
WIRE -608 -1152 -608 -1184
WIRE -240 -1152 -240 -1184
WIRE 384 -1152 384 -1232
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WIRE 384 -1136 384 -1152
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WIRE -240 -1040 -240 -1072
WIRE -1104 -1024 -1104 -1040
WIRE 384 -976 384 -1072
WIRE 768 -896 768 -1392
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WIRE 640 -736 432 -736
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WIRE 912 -656 832 -656
WIRE 1040 -656 912 -656
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WIRE -800 -624 -800 -656
WIRE -512 -624 -512 -656
WIRE -208 -624 -208 -656
WIRE 96 -624 96 -656
WIRE 832 -624 832 -656
WIRE 1040 -624 1040 -656
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WIRE -512 -512 -512 -544
WIRE -208 -512 -208 -544
WIRE 96 -512 96 -544
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WIRE 832 -512 768 -512
WIRE 912 -512 960 -608
WIRE 912 -512 832 -512
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WIRE 1040 -512 1040 -528
WIRE 1040 -512 960 -512
WIRE 1120 -512 1120 -528
WIRE 1120 -512 1040 -512
WIRE 768 -432 768 -512
WIRE 912 -432 768 -432
WIRE 1120 -432 1120 -512
WIRE 1120 -432 1008 -432
WIRE 1120 -416 1120 -432
WIRE 640 -384 608 -384
WIRE 880 -384 640 -384
WIRE 928 -384 880 -384
WIRE 1056 -384 928 -384
WIRE 1296 -384 1056 -384
WIRE 880 -368 880 -384
WIRE 1056 -368 1056 -384
WIRE 768 -352 768 -432
WIRE 768 -320 768 -352
WIRE 800 -320 768 -320
WIRE 944 -320 896 -320
WIRE 976 -320 944 -320
WIRE 1120 -320 1120 -416
WIRE 1120 -320 1072 -320
WIRE 1312 -304 1312 -528
WIRE -4432 -288 -4432 -320
WIRE 944 -272 944 -320
WIRE -4480 -256 -4512 -256
WIRE -4224 -240 -4432 -240
WIRE -4048 -240 -4128 -240
WIRE -4512 -208 -4512 -256
WIRE -4512 -208 -4592 -208
WIRE 768 -192 768 -320
WIRE 832 -192 768 -192
WIRE 912 -192 832 -192
WIRE 1040 -192 976 -192
WIRE 1120 -192 1120 -320
WIRE 1120 -192 1040 -192
WIRE 832 -176 832 -192
WIRE 1040 -176 1040 -192
WIRE -4512 -160 -4512 -208
WIRE -4480 -160 -4512 -160
WIRE -4432 -160 -4432 -192
WIRE 912 -96 976 -192
WIRE 912 -96 880 -96
WIRE 976 -96 912 -192
WIRE 992 -96 976 -96
WIRE 832 -48 832 -80
WIRE 832 -48 720 -48
WIRE 960 -48 832 -48
WIRE 1040 -48 1040 -80
WIRE 1040 -48 960 -48
WIRE 672 32 416 32
WIRE -4432 64 -4432 32
WIRE -4480 96 -4512 96
WIRE -4224 112 -4432 112
WIRE -4048 112 -4128 112
WIRE 1312 128 1312 -208
WIRE 1312 128 1200 128
WIRE -4512 144 -4512 96
WIRE -4512 144 -4592 144
WIRE 1200 160 1200 128
WIRE -4512 192 -4512 144
WIRE -4480 192 -4512 192
WIRE -4432 192 -4432 160
WIRE 1088 272 880 272
WIRE 1152 272 1152 240
WIRE 1152 272 1088 272
WIRE 1200 304 1200 256
WIRE 1200 320 1200 304
WIRE 1312 432 1312 128
FLAG -1104 -1024 0
FLAG -1104 -1136 Eq
FLAG 720 0 0
FLAG -608 -1040 0
FLAG -608 -1184 sense_P
FLAG 1040 -128 0
FLAG 832 -128 0
FLAG 960 -432 0
FLAG 848 -320 0
FLAG 1024 -320 0
FLAG 640 -384 Eq
FLAG 944 -272 VDDby2
FLAG 416 32 sense_N
FLAG 720 48 0
FLAG 768 -352 bitline0
FLAG 1120 -416 bitline1
FLAG 624 -1312 0
FLAG 384 -1152 mb0
FLAG 304 -1280 ra0
FLAG 1200 208 0
FLAG 1200 304 mb3
FLAG 1088 272 ra3
FLAG -1392 -1552 0
FLAG -1392 -1664 ra0
FLAG 688 -704 VDD
FLAG 1040 -576 VDD
FLAG 832 -576 VDD
FLAG 688 -752 VDD
FLAG 432 -736 sense_p
FLAG 912 -656 ACT
FLAG 960 -48 NLAT
FLAG -240 -1040 0
FLAG -240 -1184 sense_N
FLAG -1584 -1152 ra3
FLAG -1584 -1040 0
FLAG -800 -512 0
FLAG -800 -656 VDD
FLAG -512 -512 0
FLAG -512 -656 VDDby2
FLAG 384 -976 PV
FLAG -208 -512 0
FLAG -208 -656 PV
FLAG 1200 384 PV
FLAG 96 -512 0
FLAG 96 -656 ISO
FLAG -4432 -144 0
FLAG -4672 -592 0
FLAG -4672 -672 WR_VDD
FLAG -4432 -336 WR_VDD
FLAG -4592 -208 WR_0
FLAG -4432 -592 0
FLAG -4432 -672 WR_0
FLAG -4160 -592 0
FLAG -4160 -672 WR_1
FLAG -4176 -240 0
FLAG -4208 -288 CSEL
FLAG -4432 208 0
FLAG -4432 16 WR_VDD
FLAG -4592 144 WR_1
FLAG -4176 112 0
FLAG -4208 64 CSEL
FLAG -4048 -240 bitline0
FLAG -4048 112 bitline1
FLAG -3824 -560 0
FLAG -3824 -736 CSEL
SYMBOL nmos4 672 -48 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL voltage -1104 -1136 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V_EQ
SYMATTR Value PULSE(0 {core_voltage*1} 0 0.5n 0.5n 18n 100n 2)
SYMBOL voltage -608 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act} 0.5n 0.5n 75n)
SYMATTR InstName V_SP
SYMBOL nmos4 992 -176 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL nmos4 880 -176 M0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL nmos4 1008 -384 M270
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL nmos4 800 -368 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 976 -368 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 576 -1360 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M7
SYMATTR Value nmoslp
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 368 -1136 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + {cell_init_voltage}}
SYMBOL nmos4 1152 160 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M8
SYMATTR Value nmoslp
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1184 320 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMATTR SpiceLine IC={-plate_voltage + 0.02*1.2}
SYMBOL voltage -1392 -1664 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName V_RA0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, 0.00)} 20n 0.5n 0.5n 75n)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL pmos4 640 -656 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL pmos4 992 -528 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL pmos4 880 -528 R180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL voltage -240 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {core_voltage -3n} {20n + nsense_act} 0.5n 0.5n 75n)
SYMATTR InstName V_SN
SYMBOL voltage -1584 -1152 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName V_RA3
SYMATTR Value 0
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -800 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL voltage -512 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage/2}
SYMATTR InstName V_HALFVDD
SYMBOL voltage -208 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {plate_voltage}
SYMATTR InstName V_PV
SYMBOL voltage 96 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value 0
SYMATTR InstName V_ISO
SYMBOL bitline 768 -848 R90
SYMATTR InstName X1
SYMATTR SpiceLine R={mc(40,0.05)} C={mc(bitline_cap / 512, 0.05)}
SYMBOL bitline 1312 -256 R90
SYMATTR InstName X2
SYMATTR SpiceLine R={mc(40,0.05)} C={mc(bitline_cap / 512, 0.05)}
SYMBOL nmos4 -4480 -240 R0
SYMATTR InstName M47
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL pmos4 -4480 -336 R0
SYMATTR InstName M54
SYMATTR Value2 l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
SYMBOL voltage -4672 -688 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V_WRVDD
SYMATTR Value {core_voltage}
SYMBOL voltage -4432 -688 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V_WR0
SYMATTR Value {core_voltage}
SYMBOL voltage -4160 -688 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V_WR1
SYMATTR Value 0
SYMBOL nmos4 -4128 -288 R90
WINDOW 0 56 32 Invisible 2
WINDOW 3 0 101 VRight 2
SYMATTR InstName M55
SYMATTR Value2 l={mc(SA_CSEL_L, process_var)} w={mc(SA_CSEL_W, process_var)}
SYMBOL nmos4 -4480 112 R0
SYMATTR InstName M56
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL pmos4 -4480 16 R0
SYMATTR InstName M57
SYMATTR Value2 l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
SYMBOL nmos4 -4128 64 R90
WINDOW 0 56 32 Invisible 2
WINDOW 3 0 101 VRight 2
SYMATTR InstName M58
SYMATTR Value2 l={mc(SA_CSEL_L, process_var)} w={mc(SA_CSEL_W, process_var)}
SYMBOL voltage -3824 -656 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -226 48 Left 2
SYMATTR Value PULSE(0 2.5 75n 0.5n 0.5n 15n)
SYMATTR InstName V_CSEL
TEXT -376 136 Left 2 !.include ./transistor_model.pm
TEXT 800 -952 VLeft 2 ;Bitline to array0
TEXT 1296 96 VLeft 2 ;Bitline to array1
TEXT -448 104 Left 2 !.tran 120ns uic
TEXT -392 216 Left 2 ;Plot Eq, ra0, ra1, bitline0+1.25, bitline1+1.25, sense_n+2.5, and sense_p+3.75
TEXT 48 -1296 Left 2 ;Word line in array 0
TEXT 832 256 Left 2 ;Word line in array 1
TEXT -368 168 Left 2 ;.step param X 0.0v 1.5v 0.1v
TEXT -832 80 Left 2 !.param process_var=0.05
TEXT -832 40 Left 2 !.step param run 1 10000 1
TEXT -832 456 Left 2 !.param cell_cap={24fF * cell_cap_factor}
TEXT -832 496 Left 2 !.param bitline_cap={70f}
TEXT -920 168 Left 2 ;DRAM Circuit Parameters
TEXT -832 536 Left 2 !.param access_tran_L={85nm*access_tran_L_factor}
TEXT -832 576 Left 2 !.param access_tran_W={55nm*access_tran_W_factor}
TEXT -824 1264 Left 2 !.param bitline_R=R_per_cell*cells_per_BL
TEXT -552 1200 Left 2 ;ohm
TEXT -824 1200 Left 2 !.param R_per_cell=60
TEXT -824 1168 Left 2 ;Bitline Resistance
TEXT -824 760 Left 2 !.param SA_nmos_L={160nm*SA_nmos_L_factor}
TEXT -824 784 Left 2 !.param SA_nmos_W={1900nm*SA_nmos_W_factor}
TEXT -824 816 Left 2 !.param SA_pmos_L={160nm*SA_pmos_L_factor}
TEXT -824 840 Left 2 !.param SA_pmos_W={1330nm*SA_pmos_W_factor}
TEXT -824 880 Left 2 !.param SA_eq_L=96.3n
TEXT -824 904 Left 2 !.param SA_eq_W=541n
TEXT -824 944 Left 2 !.param SA_nset_L={255nm*SA_nset_L_factor}
TEXT -824 968 Left 2 !.param SA_nset_W={220nm*SA_nset_W_factor}
TEXT -824 1008 Left 2 !.param SA_pset_L={255nm*SA_pset_L_factor}
TEXT -824 1032 Left 2 !.param SA_pset_W={220nm*SA_pset_W_factor}
TEXT -824 1232 Left 2 !.param cells_per_BL=512
TEXT -832 424 Left 2 ;Cell Array
TEXT -824 728 Left 2 ;Sense Amp.
TEXT -832 224 Left 2 ;Voltage
TEXT -832 248 Left 2 !.param core_voltage=1.2V
TEXT -832 288 Left 2 !.param wordline_voltage=2.5V
TEXT -832 320 Left 2 !.param pv_modifier=0.5
TEXT -832 360 Left 2 !.param plate_voltage={core_voltage*pv_modifier}
TEXT -2080 152 Left 2 !.param psense_act=4ns
TEXT -2080 176 Left 2 !.param nsense_act=4ns
TEXT -816 1520 Left 2 ;Wordline Activation
TEXT -816 1552 Left 2 !.param wl0_act=1.0
TEXT -824 1640 Left 2 !.param tech_node=7
TEXT -576 1640 Left 2 ;1 -> 45 nm, 4 -> 32nm, 7 -> 22 nm, 9-> 16nm
TEXT -824 1608 Left 2 ;Technology Scaling
TEXT -824 1672 Left 2 !.param cell_cap_factor={0.95**tech_node}
TEXT -824 1704 Left 2 !.param bl_cap_factor={0.95**tech_node}
TEXT -824 1736 Left 2 !.param access_tran_L_factor={0.95**tech_node}
TEXT -824 1768 Left 2 !.param access_tran_W_factor={0.85**tech_node}
TEXT -824 1800 Left 2 !.param SA_nmos_L_factor={0.93**tech_node}
TEXT -824 1824 Left 2 !.param SA_nmos_W_factor={0.93**tech_node}
TEXT -824 1856 Left 2 !.param SA_pmos_L_factor={0.93**tech_node}
TEXT -824 1880 Left 2 !.param SA_pmos_W_factor={0.93**tech_node}
TEXT -824 1912 Left 2 !.param SA_nset_L_factor={0.93**tech_node}
TEXT -824 1936 Left 2 !.param SA_nset_W_factor={0.93**tech_node}
TEXT -824 1968 Left 2 !.param SA_pset_L_factor={0.93**tech_node}
TEXT -824 1992 Left 2 !.param SA_pset_W_factor={0.95**tech_node}
TEXT -824 1448 Left 2 !.param wordline_C={WL_C_per_cell*cells_per_LWL}
TEXT -824 1384 Left 2 !.param WL_C_per_cell=0.07fF
TEXT -824 1328 Left 2 ;Wordline Parasitics
TEXT -824 1352 Left 2 !.param cells_per_LWL=512
TEXT -824 1416 Left 2 !.param WL_R_per_cell=40ohm
TEXT -824 1480 Left 2 !.param wordline_R={WL_R_per_cell*cells_per_LWL}
TEXT -824 2024 Left 2 !.param WL_cap_factor={0.95**tech_node}
TEXT -824 2056 Left 2 !.param WL_res_factor={0.95**tech_node}
TEXT 248 -360 Left 2 ;.OPTIONS maxord=1\n.OPTIONS itl1=1000\n.OPTIONS itl2=1000\n.OPTIONS itl4=1000
TEXT 256 -168 Left 2 !.TEMP 85
TEXT -5352 -352 Left 2 !.param SA_nWR_L = {70n*SA_nWR_L_factor}\n.param SA_nWR_W = {840n*SA_nWR_W_factor}\n.param SA_pWR_L = {70n*SA_pWR_L_factor}\n.param SA_pWR_W = {840n*SA_pWR_W_factor}\n.param SA_CSEL_L = {70n*SA_CSEL_L_factor}\n.param SA_CSEL_W = {840n*SA_CSEL_L_factor}\n.param SA_nWR_L_factor={0.93**tech_node}\n.param SA_nWR_W_factor={0.93**tech_node}\n.param SA_pWR_L_factor={0.93**tech_node}\n.param SA_pWR_W_factor={0.93**tech_node}\n.param SA_CSEL_L_factor={0.93**tech_node}\n.param SA_CSEL_W_factor={0.93**tech_node}
TEXT 8 512 Left 2 !.param ISO_L_factor=0.3\n.param ISO_W_factor=10
TEXT -2088 72 Left 2 ;Vars
TEXT -2080 128 Left 2 !.param cell_init_voltage=0.55*1.2