diff --git a/docs/Low Dropout Regulator/design_variables/LDO_1.txt b/docs/Low Dropout Regulator/design_variables/LDO_1.txt new file mode 100644 index 0000000..167770e --- /dev/null +++ b/docs/Low Dropout Regulator/design_variables/LDO_1.txt @@ -0,0 +1,12 @@ +*Basic_LDO +.PARAM capacitor_0=2000f iload=100m ++ mosfet_11_1_l_power_pmos=0.15 mosfet_11_1_m_power_pmos=20000 ++ mosfet_11_1_w_power_pmos=5 mosfet_0_8_l_biascm_pmos=1 ++ mosfet_0_8_m_biascm_pmos=4 mosfet_0_8_w_biascm_pmos=1 ++ mosfet_10_1_l_gm2_pmos=0.5 mosfet_10_1_m_gm2_pmos=32 ++ mosfet_10_1_w_gm2_pmos=1 mosfet_17_7_l_biascm_nmos=1 ++ mosfet_17_7_m_biascm_nmos=4 mosfet_17_7_w_biascm_nmos=1 ++ mosfet_21_2_l_load2_nmos=1 mosfet_21_2_m_load2_nmos=16 ++ mosfet_21_2_w_load2_nmos=1 mosfet_8_2_l_gm1_pmos=1 ++ mosfet_8_2_m_gm1_pmos=4 mosfet_8_2_w_gm1_pmos=1 current_0_bias=5u ++ cload=50p vcm=200m vdd=1 \ No newline at end of file diff --git a/docs/Low Dropout Regulator/ldo_testbench/TB_LDO_ACDC.cir b/docs/Low Dropout Regulator/ldo_testbench/TB_LDO_ACDC.cir new file mode 100644 index 0000000..099441d --- /dev/null +++ b/docs/Low Dropout Regulator/ldo_testbench/TB_LDO_ACDC.cir @@ -0,0 +1,97 @@ +Test LDO ACDC + +*.OPTIONS RELTOL=.0001 +*************************************** +* Step 1: Replace circuit netlist here. +*************************************** +.include ./ldo_spice_netlist/LDO_1.txt +.include ./ldo_spice_parameter/LDO_1.txt + +.param mc_mm_switch=0 +.param mc_pr_switch=0 + +.include ./mosfet_model/sky130_pdk/libs.tech/ngspice/corners/tt.spice +*.include.\mosfet_model\sky130_pdk\libs.tech\ngspice\r+c\res_typical__cap_typical.spice +*.include.\mosfet_model\sky130_pdk\libs.tech\ngspice\r+c\res_typical__cap_typical__lin.spice +*.include.\mosfet_model\sky130_pdk\libs.tech\ngspice\corners\tt\specialized_cells.spice + + +.PARAM supply_voltage = 1.8 +.PARAM Vref = 0.4 +.PARAM PARAM_CLOAD =100.00p +.PARAM PARAM_ILOAD =10m + +V1 vdd 0 'supply_voltage' +V2 vss 0 0 + +Vindc vref_in 0 'Vref' +Vin signal_in 0 dc 'Vref' ac 1 sin('Vref' 100m 500) + +* Circuit List: +* Basic_LDO + + +* XLDO gnda vdda vinn vout vddp vfb vinp +* | | | | | | | +* | | | | | | Non-inverting input +* | | | | | Feedback voltage +* | | | | Supply of the Power transistor +* | | | Output +* | | Inverting Input +* | Positive Supply +* Negative Supply + +*************************************** +* Step 3: Replace circuit name below. +* e.g. Basic_LDO -> DFCFC_LDO +*************************************** +* ADM TB +Xldo1 vss vdd vref_in vout1 vdd vfb1 vinp1 Basic_LDO +Lfb vinp1 vfb1 1T +Cfb vinp1 signal_in 1T +Cload1 vout1 0 'PARAM_CLOAD' +Iload1 vout1 0 'PARAM_ILOAD' +.meas ac dcgain find vdb(vout1) at = 0.1 +.meas ac gain_bandwidth_product when vdb(vout1)=0 +.meas ac phase_in_rad find vp(vout1) when vdb(vout1)=0 +.meas ac phase_in_deg param='phase_in_rad*180/3.1416' + +* PSRR TB +VVDDApsrr vddpsrr 0 'supply_voltage' AC=1 +xop2 vss vddpsrr vref_in ppsr1 vddpsrr vfb2 vfb2 Basic_LDO +Cload2 ppsr1 0 'PARAM_CLOAD' +Iload2 ppsr1 0 'PARAM_ILOAD' +.measure ac DCPSRp find vdb(ppsr1) at = 0.1 + +* DC ALL TB +VVDDdc VDDdc 0 'supply_voltage' +VVDDdc2 vddpass 0 'supply_voltage' +xop3 vss vdddc vref_in vout6 vddpass vfb3 vfb3 Basic_LDO +Cload3 vout6 0 'PARAM_CLOAD' +Iload3 vout6 0 'PARAM_ILOAD' + +* LR meas +.measure dc maxval MAX V(vout6) from=5m to=55m +.measure dc minval MIN V(vout6) from=5m to=55m +.measure dc avgval AVG V(vout6) from=5m to=55m +.measure dc ppavl PP V(vout6) from=5m to=55m +.measure dc LR param='ppavl/avgval/50m' +* Power meas +.meas dc Ivdd FIND I(VVDDDC) AT=55m +.meas dc Power param='-1*Ivdd*supply_voltage' +* Vos.meas +.meas dc vout FIND V(vout6) AT=55m +.meas dc vos param = 'vout-4*Vref' + +.control + +DC Iload3 5m 55m 0.1m +plot v(vout6) + +ac dec 10 0.1 1G +plot vdb(vout1) vdb(ppsr1) +plot vp(vout1) + +.endc + +.end diff --git a/docs/Low Dropout Regulator/ldo_testbench/TB_LDO_Tran.cir b/docs/Low Dropout Regulator/ldo_testbench/TB_LDO_Tran.cir new file mode 100644 index 0000000..41673fa --- /dev/null +++ b/docs/Low Dropout Regulator/ldo_testbench/TB_LDO_Tran.cir @@ -0,0 +1,77 @@ +Test LDO Tran + +*.OPTIONS RELTOL=.0001 +*************************************** +* Step 1: Replace circuit netlist here. +*************************************** +.include ./ldo_spice_netlist/LDO_1.txt +.include ./ldo_spice_parameter/LDO_1.txt + +.param mc_mm_switch=0 +.param mc_pr_switch=0 + +.include ./mosfet_model/sky130_pdk/libs.tech/ngspice/corners/tt.spice +*.include.\mosfet_model\sky130_pdk\libs.tech\ngspice\r+c\res_typical__cap_typical.spice +*.include.\mosfet_model\sky130_pdk\libs.tech\ngspice\r+c\res_typical__cap_typical__lin.spice +*.include.\mosfet_model\sky130_pdk\libs.tech\ngspice\corners\tt\specialized_cells.spice + +.PARAM supply_voltage = 1.8 +.PARAM Vref = 0.4 +.PARAM PARAM_CLOAD =100.00p +.PARAM PARAM_ILOAD =10n +.PARAM val0 = 1n +.PARAM val1 = 5m +.PARAM GBW_ideal = 5e4 +.PARAM STEP_TIME = '10/GBW_ideal' + + +V1 vdd 0 'supply_voltage' +V2 vss 0 0 + +Vindc vref_in 0 'Vref' + +* Circuit List: +* Basic_LDO + + +* XLDO gnda vdda vinn vout vddp vfb vinp +* | | | | | | | +* | | | | | | Non-inverting input +* | | | | | Feedback voltage +* | | | | Supply of the Power transistor +* | | | Output +* | | Inverting Input +* | Positive Supply +* Negative Supply + +*************************************** +* Step 3: Replace circuit name below. +* e.g. Basic_LDO -> DFCFC_LDO +*************************************** +* Tran TB +Xldo1 vss vdd vref_in vout1 vdd vfb1 vfb1 Basic_LDO +Cload1 vout1 0 'PARAM_CLOAD' +Iload1 vout1 0 pulse('val0' 'val1' 1u 1p 1p '1*STEP_TIME' 1) + +.meas tran v_min MIN v(vout1) from=900n to='900n+STEP_TIME' +.meas tran v_max MAX v(vout1) from='900n+STEP_TIME' to=1m +.meas tran v_undershoot param='4*vref - v_min' +.meas tran v_overshoot param='v_max - 4*vref' + +* Voltage Regulation meas +.measure dc maxval MAX V(vout1) from='0.9*Vref*4' to='1.1*Vref*4' +.measure dc minval MIN V(vout1) from='0.9*Vref*4' to='1.1*Vref*4' +.measure dc avgval AVG V(vout1) from='0.9*Vref*4' to='1.1*Vref*4' +.measure dc ppavl PP V(vout1) from='0.9*Vref*4' to='1.1*Vref*4' +.measure dc VR param='ppavl/avgval/0.8/Vref' + +.control + +tran 1u 1m +dc v1 0 2 0.1 +plot v(vout1) +write tran.dat v(vout1) + +.endc + +.end diff --git a/docs/Low Dropout Regulator/spice_netlist/LDO_1.txt b/docs/Low Dropout Regulator/spice_netlist/LDO_1.txt new file mode 100644 index 0000000..76ab54a --- /dev/null +++ b/docs/Low Dropout Regulator/spice_netlist/LDO_1.txt @@ -0,0 +1,30 @@ +.subckt Basic_LDO gnda vdda vinn vout vddp vfb vinp +xm24 net1 net116 vdda vdda sky130_fd_pr__pfet_01v8 l=mosfet_0_8_l_biascm_pmos w='mosfet_0_8_w_biascm_pmos*1' m=mosfet_0_8_m_biascm_pmos +xm0 net116 net116 vdda vdda sky130_fd_pr__pfet_01v8 l=mosfet_0_8_l_biascm_pmos w='mosfet_0_8_w_biascm_pmos*1' m=mosfet_0_8_m_biascm_pmos +xm1 vb4 net116 vdda vdda sky130_fd_pr__pfet_01v8 l=mosfet_0_8_l_biascm_pmos w='mosfet_0_8_w_biascm_pmos*1' m=mosfet_0_8_m_biascm_pmos +xm2 dm_1 net116 vdda vdda sky130_fd_pr__pfet_01v8 l=mosfet_0_8_l_biascm_pmos w='mosfet_0_8_w_biascm_pmos*1' m=mosfet_0_8_m_biascm_pmos +xm3 vb3 net116 vdda vdda sky130_fd_pr__pfet_01v8 l=mosfet_0_8_l_biascm_pmos w='mosfet_0_8_w_biascm_pmos*1' m=mosfet_0_8_m_biascm_pmos +xm4 net20 net116 vdda vdda sky130_fd_pr__pfet_01v8 l=mosfet_0_8_l_biascm_pmos w='mosfet_0_8_w_biascm_pmos*1' m='2*mosfet_0_8_m_biascm_pmos' +xm8 dm_2 vinp net20 net20 sky130_fd_pr__pfet_01v8 l=mosfet_8_2_l_gm1_pmos w='mosfet_8_2_w_gm1_pmos*1' m=mosfet_8_2_m_gm1_pmos +xm9 net106 vinn net20 net20 sky130_fd_pr__pfet_01v8 l=mosfet_8_2_l_gm1_pmos w='mosfet_8_2_w_gm1_pmos*1' m=mosfet_8_2_m_gm1_pmos +xm5 voutn voutn vdda vdda sky130_fd_pr__pfet_01v8 l=mosfet_0_8_l_biascm_pmos w='mosfet_0_8_w_biascm_pmos*1' m=mosfet_0_8_m_biascm_pmos +xm6 net10 voutn vdda vdda sky130_fd_pr__pfet_01v8 l=mosfet_0_8_l_biascm_pmos w='mosfet_0_8_w_biascm_pmos*1' m=mosfet_0_8_m_biascm_pmos +xm10 net12 net10 net1 net1 sky130_fd_pr__pfet_01v8 l=mosfet_10_1_l_gm2_pmos w='mosfet_10_1_w_gm2_pmos*1' m=mosfet_10_1_m_gm2_pmos +xm7 net7 net116 vdda vdda sky130_fd_pr__pfet_01v8 l=mosfet_0_8_l_biascm_pmos w='mosfet_0_8_w_biascm_pmos*1' m=mosfet_0_8_m_biascm_pmos +xm11 vout net1 vddp vddp sky130_fd_pr__pfet_01v8 l=mosfet_11_1_l_power_pmos w='mosfet_11_1_w_power_pmos*1' m=mosfet_11_1_m_power_pmos +xm13 dm_1 vb3 net31 gnda sky130_fd_pr__nfet_01v8 l=mosfet_17_7_l_biascm_nmos w='mosfet_17_7_w_biascm_nmos*1' m='mosfet_17_7_m_biascm_nmos*4' +xm18 net31 vb4 gnda gnda sky130_fd_pr__nfet_01v8 l=mosfet_17_7_l_biascm_nmos w='mosfet_17_7_w_biascm_nmos*1' m='mosfet_17_7_m_biascm_nmos*4' +xm12 vb4 vb3 net28 gnda sky130_fd_pr__nfet_01v8 l=mosfet_17_7_l_biascm_nmos w='mosfet_17_7_w_biascm_nmos*1' m='mosfet_17_7_m_biascm_nmos*4' +xm14 vb3 vb3 gnda gnda sky130_fd_pr__nfet_01v8 l=mosfet_17_7_l_biascm_nmos w='mosfet_17_7_w_biascm_nmos*1' m=mosfet_17_7_m_biascm_nmos +xm17 net28 vb4 gnda gnda sky130_fd_pr__nfet_01v8 l=mosfet_17_7_l_biascm_nmos w='mosfet_17_7_w_biascm_nmos*1' m='mosfet_17_7_m_biascm_nmos*4' +xm16 net10 vb3 net106 gnda sky130_fd_pr__nfet_01v8 l=mosfet_17_7_l_biascm_nmos w='mosfet_17_7_w_biascm_nmos*1' m='mosfet_17_7_m_biascm_nmos*4' +xm20 net106 vb4 gnda gnda sky130_fd_pr__nfet_01v8 l=mosfet_17_7_l_biascm_nmos w='mosfet_17_7_w_biascm_nmos*1' m='mosfet_17_7_m_biascm_nmos*8' +xm15 voutn vb3 dm_2 gnda sky130_fd_pr__nfet_01v8 l=mosfet_17_7_l_biascm_nmos w='mosfet_17_7_w_biascm_nmos*1' m='mosfet_17_7_m_biascm_nmos*4' +xm19 dm_2 vb4 gnda gnda sky130_fd_pr__nfet_01v8 l=mosfet_17_7_l_biascm_nmos w='mosfet_17_7_w_biascm_nmos*1' m='mosfet_17_7_m_biascm_nmos*8' +xm21 net12 net7 gnda gnda sky130_fd_pr__nfet_01v8 l=mosfet_21_2_l_load2_nmos w='mosfet_21_2_w_load2_nmos*1' m=mosfet_21_2_m_load2_nmos +xm22 net7 net7 gnda gnda sky130_fd_pr__nfet_01v8 l=mosfet_21_2_l_load2_nmos w='mosfet_21_2_w_load2_nmos*1' m=mosfet_21_2_m_load2_nmos +i0 net116 gnda DC='current_0_bias' +r1 vout vfb 300e3 +r0 vfb gnda 100e3 +c0 net106 vout 'capacitor_0' +.ends Basic_LDO \ No newline at end of file