huffman.v

//----------------------------------------------------------------------------//
// Generated by LegUp High-Level Synthesis Tool Version 4.0 (http://legup.org)
// Compiled: Sun Jul 26 12:56:54 2015
// University of Toronto
// For research and academic purposes only. Commercial use is prohibited.
// Please send bugs to: legup@eecg.toronto.edu
// Date: Wed Aug  1 17:41:31 2018
//----------------------------------------------------------------------------//

`define MEMORY_CONTROLLER_ADDR_SIZE 32
`define MEMORY_CONTROLLER_DATA_SIZE 64
// Number of RAM elements: 4
`define MEMORY_CONTROLLER_TAG_SIZE 9
// @alfabeto = internal global [128 x %struct.node] zeroinitializer, align 4
`define TAG_g_alfabeto `MEMORY_CONTROLLER_TAG_SIZE'd3
`define TAG_g_alfabeto_a {`TAG_g_alfabeto, 23'd0}
// @heap = internal unnamed_addr global [129 x %struct.node*] zeroinitializer, align 4
`define TAG_g_heap `MEMORY_CONTROLLER_TAG_SIZE'd5
`define TAG_g_heap_a {`TAG_g_heap, 23'd0}
// @intermediarios = internal global [128 x %struct.node] zeroinitializer, align 4
`define TAG_g_intermediarios `MEMORY_CONTROLLER_TAG_SIZE'd4
`define TAG_g_intermediarios_a {`TAG_g_intermediarios, 23'd0}
// @texto = internal unnamed_addr constant [682 x i8] c"Lorem ipsum dolor sit amet, consectetur adipiscing elit. Praesent eget risus vitae massa semper aliquam quis mattis quam. Morbi vitae tortor tempus...
`define TAG_g_texto `MEMORY_CONTROLLER_TAG_SIZE'd2
`define TAG_g_texto_a {`TAG_g_texto, 23'd0}

// Turn off warning 'ignoring unsupported system task'
// altera message_off 10175

`timescale 1 ns / 1 ns
module top
	(
		clk,
		reset,
		start,
		finish,
		waitrequest,
		return_val
	);
output led_huffman;
input clk;
input reset;
input start;
output wire finish;
input waitrequest;
output wire [31:0] return_val;
wire memory_controller_waitrequest;
wire memory_controller_enable_a;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_a;
wire memory_controller_write_enable_a;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in_a;
wire [1:0] memory_controller_size_a;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out_a;

wire memory_controller_enable_b;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_b;
wire memory_controller_write_enable_b;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in_b;
wire [1:0] memory_controller_size_b;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out_b;

/* synthesis translate_off */
assign memory_controller_waitrequest = waitrequest;
/* synthesis translate_on */

memory_controller memory_controller_inst (
	.clk( clk ),
	.memory_controller_enable_a( memory_controller_enable_a ),
	.memory_controller_enable_b( memory_controller_enable_b ),
	.memory_controller_address_a( memory_controller_address_a ),
	.memory_controller_address_b( memory_controller_address_b ),
	.memory_controller_write_enable_a( memory_controller_write_enable_a ),
	.memory_controller_write_enable_b( memory_controller_write_enable_b ),
	.memory_controller_in_a( memory_controller_in_a ),
	.memory_controller_in_b( memory_controller_in_b ),
	.memory_controller_size_a( memory_controller_size_a ),
	.memory_controller_size_b( memory_controller_size_b ),
	.memory_controller_waitrequest( memory_controller_waitrequest ),
	.memory_controller_out_reg_a( memory_controller_out_a ),
	.memory_controller_out_reg_b( memory_controller_out_b )
);

main main_inst(
	.clk( clk ),
	.clk2x( clk2x ),
	.clk1x_follower( clk1x_follower ),
	.reset( reset ),
	.start( start ),
	.finish( finish ),
	.return_val( return_val ),
	.memory_controller_waitrequest(memory_controller_waitrequest),
	.memory_controller_enable_a(memory_controller_enable_a),
	.memory_controller_address_a(memory_controller_address_a),
	.memory_controller_write_enable_a(memory_controller_write_enable_a),
	.memory_controller_in_a(memory_controller_in_a),
	.memory_controller_size_a(memory_controller_size_a),
	.memory_controller_out_a(memory_controller_out_a),
	.memory_controller_enable_b(memory_controller_enable_b),
	.memory_controller_address_b(memory_controller_address_b),
	.memory_controller_write_enable_b(memory_controller_write_enable_b),
	.memory_controller_in_b(memory_controller_in_b),
	.memory_controller_size_b(memory_controller_size_b),
	.memory_controller_out_b(memory_controller_out_b)
);

endmodule

`timescale 1 ns / 1 ns
module memory_controller
(
	clk,
	memory_controller_address_a,
	memory_controller_address_b,
	memory_controller_enable_a,
	memory_controller_enable_b,
	memory_controller_write_enable_a,
	memory_controller_write_enable_b,
	memory_controller_in_a,
	memory_controller_in_b,
	memory_controller_size_a,
	memory_controller_size_b,
	memory_controller_waitrequest,
	memory_controller_out_reg_a,
	memory_controller_out_reg_b
);

parameter latency = 2;

parameter ram_latency = latency-1;

integer j;

input clk;
input memory_controller_waitrequest;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_a;
input memory_controller_enable_a;
input memory_controller_write_enable_a;
input [64-1:0] memory_controller_in_a;
input [1:0] memory_controller_size_a;
output reg [64-1:0] memory_controller_out_reg_a;
reg [64-1:0] memory_controller_out_prev_a;
reg [64-1:0] memory_controller_out_a;

reg memory_controller_enable_reg_a;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_b;
input memory_controller_enable_b;
input memory_controller_write_enable_b;
input [64-1:0] memory_controller_in_b;
input [1:0] memory_controller_size_b;
output reg [64-1:0] memory_controller_out_reg_b;
reg [64-1:0] memory_controller_out_prev_b;
reg [64-1:0] memory_controller_out_b;

reg memory_controller_enable_reg_b;

reg [9:0] texto_address_a;
reg [9:0] texto_address_b;
reg texto_write_enable_a;
reg texto_write_enable_b;
reg [7:0] texto_in_a;
reg [7:0] texto_in_b;
wire [7:0] texto_out_a;
wire [7:0] texto_out_b;

// @texto = internal unnamed_addr constant [682 x i8] c"Lorem ipsum dolor sit amet, consectetur adipiscing elit. Praesent eget risus vitae massa semper aliquam quis mattis quam. Morbi vitae tortor tempus...
rom_dual_port texto (
	.clk( clk ),
	.clken( !memory_controller_waitrequest ),
	.address_a( texto_address_a ),
	.address_b( texto_address_b ),
	.q_a( texto_out_a ),
	.q_b( texto_out_b)
);
defparam texto.width_a = 8;
defparam texto.width_b = 8;
defparam texto.widthad_a = 10;
defparam texto.widthad_b = 10;
defparam texto.numwords_a = 682;
defparam texto.numwords_b = 682;
defparam texto.latency = ram_latency;
defparam texto.init_file = "texto.mif";

reg [7:0] alfabeto_address_a;
reg [7:0] alfabeto_address_b;
reg alfabeto_write_enable_a;
reg alfabeto_write_enable_b;
reg [63:0] alfabeto_in_a;
reg [63:0] alfabeto_in_b;
wire [63:0] alfabeto_out_a;
wire [63:0] alfabeto_out_b;
reg [8-1:0] alfabeto_byteena_a;
reg [8-1:0] alfabeto_byteena_b;

// @alfabeto = internal global [128 x %struct.node] zeroinitializer, align 4
ram_dual_port alfabeto (
	.clk( clk ),
	.clken( !memory_controller_waitrequest ),
	.address_a( alfabeto_address_a ),
	.address_b( alfabeto_address_b ),
	.wren_a( alfabeto_write_enable_a ),
	.wren_b( alfabeto_write_enable_b ),
	.data_a( alfabeto_in_a ),
	.data_b( alfabeto_in_b ),
	.byteena_a( alfabeto_byteena_a ),
	.byteena_b( alfabeto_byteena_b ),
	.q_a( alfabeto_out_a ),
	.q_b( alfabeto_out_b)
);
defparam alfabeto.width_a = 64;
defparam alfabeto.width_b = 64;
defparam alfabeto.widthad_a = 8;
defparam alfabeto.widthad_b = 8;
defparam alfabeto.width_be_a = 8;
defparam alfabeto.width_be_b = 8;
defparam alfabeto.numwords_a = 256;
defparam alfabeto.numwords_b = 256;
defparam alfabeto.latency = ram_latency;
defparam alfabeto.init_file = "alfabeto.mif";

reg [7:0] intermediarios_address_a;
reg [7:0] intermediarios_address_b;
reg intermediarios_write_enable_a;
reg intermediarios_write_enable_b;
reg [63:0] intermediarios_in_a;
reg [63:0] intermediarios_in_b;
wire [63:0] intermediarios_out_a;
wire [63:0] intermediarios_out_b;
reg [8-1:0] intermediarios_byteena_a;
reg [8-1:0] intermediarios_byteena_b;

// @intermediarios = internal global [128 x %struct.node] zeroinitializer, align 4
ram_dual_port intermediarios (
	.clk( clk ),
	.clken( !memory_controller_waitrequest ),
	.address_a( intermediarios_address_a ),
	.address_b( intermediarios_address_b ),
	.wren_a( intermediarios_write_enable_a ),
	.wren_b( intermediarios_write_enable_b ),
	.data_a( intermediarios_in_a ),
	.data_b( intermediarios_in_b ),
	.byteena_a( intermediarios_byteena_a ),
	.byteena_b( intermediarios_byteena_b ),
	.q_a( intermediarios_out_a ),
	.q_b( intermediarios_out_b)
);
defparam intermediarios.width_a = 64;
defparam intermediarios.width_b = 64;
defparam intermediarios.widthad_a = 8;
defparam intermediarios.widthad_b = 8;
defparam intermediarios.width_be_a = 8;
defparam intermediarios.width_be_b = 8;
defparam intermediarios.numwords_a = 256;
defparam intermediarios.numwords_b = 256;
defparam intermediarios.latency = ram_latency;
defparam intermediarios.init_file = "intermediarios.mif";

reg [7:0] heap_address_a;
reg [7:0] heap_address_b;
reg heap_write_enable_a;
reg heap_write_enable_b;
reg [31:0] heap_in_a;
reg [31:0] heap_in_b;
wire [31:0] heap_out_a;
wire [31:0] heap_out_b;

// @heap = internal unnamed_addr global [129 x %struct.node*] zeroinitializer, align 4
ram_dual_port heap (
	.clk( clk ),
	.clken( !memory_controller_waitrequest ),
	.address_a( heap_address_a ),
	.address_b( heap_address_b ),
	.wren_a( heap_write_enable_a ),
	.wren_b( heap_write_enable_b ),
	.data_a( heap_in_a ),
	.data_b( heap_in_b ),
	.byteena_a( 1'b1 ),
	.byteena_b( 1'b1 ),
	.q_a( heap_out_a ),
	.q_b( heap_out_b)
);
defparam heap.width_a = 32;
defparam heap.width_b = 32;
defparam heap.widthad_a = 8;
defparam heap.widthad_b = 8;
defparam heap.width_be_a = 1;
defparam heap.width_be_b = 1;
defparam heap.numwords_a = 129;
defparam heap.numwords_b = 129;
defparam heap.latency = ram_latency;
defparam heap.init_file = "heap.mif";
wire [`MEMORY_CONTROLLER_TAG_SIZE-1:0] tag_a;
assign tag_a = memory_controller_address_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:`MEMORY_CONTROLLER_ADDR_SIZE-`MEMORY_CONTROLLER_TAG_SIZE];
reg [2:0] prevAddr_a;
reg [1:0] prevSize_a;
reg [2:0] prevSize_a_and;

always @(posedge clk)
if (!memory_controller_waitrequest)
begin
	prevAddr_a <= memory_controller_address_a[2:0];
	prevSize_a <= memory_controller_size_a;
end
wire [`MEMORY_CONTROLLER_TAG_SIZE-1:0] tag_b;
assign tag_b = memory_controller_address_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:`MEMORY_CONTROLLER_ADDR_SIZE-`MEMORY_CONTROLLER_TAG_SIZE];
reg [2:0] prevAddr_b;
reg [1:0] prevSize_b;
reg [2:0] prevSize_b_and;

always @(posedge clk)
if (!memory_controller_waitrequest)
begin
	prevAddr_b <= memory_controller_address_b[2:0];
	prevSize_b <= memory_controller_size_b;
end

reg [2:0] select_not_struct_a;

wire select_texto_a;
assign select_texto_a = (tag_a == `TAG_g_texto);
reg [ram_latency:0] select_texto_reg_a;
wire [7:0] memory_controller_texto_out_a;
assign memory_controller_texto_out_a = {8{ select_texto_reg_a[ram_latency]}} & texto_out_a;

wire select_alfabeto_a;
assign select_alfabeto_a = (tag_a == `TAG_g_alfabeto);
reg [ram_latency:0] select_alfabeto_reg_a;
reg [63:0] memory_controller_alfabeto_out_a;
wire [63:0] memory_controller_alfabeto_out_struct_a;
assign memory_controller_alfabeto_out_struct_a = {64{ select_alfabeto_reg_a[ram_latency]}} & alfabeto_out_a;

wire select_intermediarios_a;
assign select_intermediarios_a = (tag_a == `TAG_g_intermediarios);
reg [ram_latency:0] select_intermediarios_reg_a;
reg [63:0] memory_controller_intermediarios_out_a;
wire [63:0] memory_controller_intermediarios_out_struct_a;
assign memory_controller_intermediarios_out_struct_a = {64{ select_intermediarios_reg_a[ram_latency]}} & intermediarios_out_a;

wire select_heap_a;
assign select_heap_a = (tag_a == `TAG_g_heap);
reg [ram_latency:0] select_heap_reg_a;
wire [31:0] memory_controller_heap_out_a;
assign memory_controller_heap_out_a = {32{ select_heap_reg_a[ram_latency]}} & heap_out_a;

always @(*)
begin
	texto_address_a = memory_controller_address_a [10-1+0:0] & {10{select_texto_a}};
	texto_write_enable_a = memory_controller_write_enable_a & select_texto_a;
	texto_in_a [8-1:0] = memory_controller_in_a[8-1:0];

	alfabeto_address_a = memory_controller_address_a[11-1:3] & {8{select_alfabeto_a}};
	alfabeto_write_enable_a = memory_controller_write_enable_a & select_alfabeto_a;
				alfabeto_in_a = 0;
		case(memory_controller_size_a)
			3:
			begin
				alfabeto_in_a[64-1:0] = memory_controller_in_a[64-1:0];
				alfabeto_byteena_a = 8'b11111111;
			end
			2:
			begin
				if (memory_controller_address_a [2:2] == 0)
				begin
					alfabeto_in_a[32-1:0] = memory_controller_in_a[32-1:0];
					alfabeto_byteena_a = 8'b00001111;
				end
				else
				begin
					alfabeto_in_a[64-1:32] = memory_controller_in_a[32-1:0];
					alfabeto_byteena_a = 8'b11110000;
				end
			end
			1:
			begin
				case (memory_controller_address_a[2:1])
					0:
					begin
						alfabeto_in_a[16-1:0] = memory_controller_in_a[16-1:0];
						alfabeto_byteena_a = 8'd3;
					end
					1:
					begin
						alfabeto_in_a[32-1:16] = memory_controller_in_a[16-1:0];
						alfabeto_byteena_a = 8'd12;
					end
					2:
					begin
						alfabeto_in_a[48-1:32] = memory_controller_in_a[16-1:0];
						alfabeto_byteena_a = 8'd48;
					end
					3:
					begin
						alfabeto_in_a[64-1:48] = memory_controller_in_a[16-1:0];
						alfabeto_byteena_a = 8'd192;
					end
				endcase
			end
			0:
				case (memory_controller_address_a[2:0])
					0:
					begin
						alfabeto_in_a[8-1:0] = memory_controller_in_a[8-1:0];
						alfabeto_byteena_a = 8'd1;
					end
					1:
					begin
						alfabeto_in_a[16-1:8] = memory_controller_in_a[8-1:0];
						alfabeto_byteena_a = 8'd2;
					end
					2:
					begin
						alfabeto_in_a[24-1:16] = memory_controller_in_a[8-1:0];
						alfabeto_byteena_a = 8'd4;
					end
					3:
					begin
						alfabeto_in_a[32-1:24] = memory_controller_in_a[8-1:0];
						alfabeto_byteena_a = 8'd8;
					end
					4:
					begin
						alfabeto_in_a[40-1:32] = memory_controller_in_a[8-1:0];
						alfabeto_byteena_a = 8'd16;
					end
					5:
					begin
						alfabeto_in_a[48-1:40] = memory_controller_in_a[8-1:0];
						alfabeto_byteena_a = 8'd32;
					end
					6:
					begin
						alfabeto_in_a[56-1:48] = memory_controller_in_a[8-1:0];
						alfabeto_byteena_a = 8'd64;
					end
					7:
					begin
						alfabeto_in_a[64-1:56] = memory_controller_in_a[8-1:0];
						alfabeto_byteena_a = 8'd128;
					end
			endcase
		endcase

	intermediarios_address_a = memory_controller_address_a[11-1:3] & {8{select_intermediarios_a}};
	intermediarios_write_enable_a = memory_controller_write_enable_a & select_intermediarios_a;
				intermediarios_in_a = 0;
		case(memory_controller_size_a)
			3:
			begin
				intermediarios_in_a[64-1:0] = memory_controller_in_a[64-1:0];
				intermediarios_byteena_a = 8'b11111111;
			end
			2:
			begin
				if (memory_controller_address_a [2:2] == 0)
				begin
					intermediarios_in_a[32-1:0] = memory_controller_in_a[32-1:0];
					intermediarios_byteena_a = 8'b00001111;
				end
				else
				begin
					intermediarios_in_a[64-1:32] = memory_controller_in_a[32-1:0];
					intermediarios_byteena_a = 8'b11110000;
				end
			end
			1:
			begin
				case (memory_controller_address_a[2:1])
					0:
					begin
						intermediarios_in_a[16-1:0] = memory_controller_in_a[16-1:0];
						intermediarios_byteena_a = 8'd3;
					end
					1:
					begin
						intermediarios_in_a[32-1:16] = memory_controller_in_a[16-1:0];
						intermediarios_byteena_a = 8'd12;
					end
					2:
					begin
						intermediarios_in_a[48-1:32] = memory_controller_in_a[16-1:0];
						intermediarios_byteena_a = 8'd48;
					end
					3:
					begin
						intermediarios_in_a[64-1:48] = memory_controller_in_a[16-1:0];
						intermediarios_byteena_a = 8'd192;
					end
				endcase
			end
			0:
				case (memory_controller_address_a[2:0])
					0:
					begin
						intermediarios_in_a[8-1:0] = memory_controller_in_a[8-1:0];
						intermediarios_byteena_a = 8'd1;
					end
					1:
					begin
						intermediarios_in_a[16-1:8] = memory_controller_in_a[8-1:0];
						intermediarios_byteena_a = 8'd2;
					end
					2:
					begin
						intermediarios_in_a[24-1:16] = memory_controller_in_a[8-1:0];
						intermediarios_byteena_a = 8'd4;
					end
					3:
					begin
						intermediarios_in_a[32-1:24] = memory_controller_in_a[8-1:0];
						intermediarios_byteena_a = 8'd8;
					end
					4:
					begin
						intermediarios_in_a[40-1:32] = memory_controller_in_a[8-1:0];
						intermediarios_byteena_a = 8'd16;
					end
					5:
					begin
						intermediarios_in_a[48-1:40] = memory_controller_in_a[8-1:0];
						intermediarios_byteena_a = 8'd32;
					end
					6:
					begin
						intermediarios_in_a[56-1:48] = memory_controller_in_a[8-1:0];
						intermediarios_byteena_a = 8'd64;
					end
					7:
					begin
						intermediarios_in_a[64-1:56] = memory_controller_in_a[8-1:0];
						intermediarios_byteena_a = 8'd128;
					end
			endcase
		endcase

	heap_address_a = memory_controller_address_a [8-1+2:2] & {8{select_heap_a}};
	heap_write_enable_a = memory_controller_write_enable_a & select_heap_a;
	heap_in_a [32-1:0] = memory_controller_in_a[32-1:0];

end
always @(*)
begin
	select_not_struct_a [2:0] = 3'b0 | {2{select_heap_reg_a[ram_latency]}};
	if (prevAddr_a[2:0] & select_not_struct_a[2:0] != 0 && memory_controller_enable_a)
	begin
		$display("Error: memory address not aligned to ram word size!");
		$finish;
	end

	prevSize_a_and[0] = prevSize_a[1] | prevSize_a[0];
	prevSize_a_and[1] = prevSize_a[1];
	prevSize_a_and[2] = prevSize_a[1] & prevSize_a[0];
	if ((prevAddr_a & prevSize_a_and) != 0 && memory_controller_enable_a)
	begin
		$display("Error: memory address not aligned to ram word size!");
		$finish;
	end
	memory_controller_alfabeto_out_a = 0;
	case(prevAddr_a)
		0: memory_controller_alfabeto_out_a[64-1:0] = memory_controller_alfabeto_out_struct_a[64-1:0];
		1: memory_controller_alfabeto_out_a[32-1:0] = memory_controller_alfabeto_out_struct_a[40-1:8];
		2: memory_controller_alfabeto_out_a[32-1:0] = memory_controller_alfabeto_out_struct_a[48-1:16];
		3: memory_controller_alfabeto_out_a[32-1:0] = memory_controller_alfabeto_out_struct_a[56-1:24];
		4: memory_controller_alfabeto_out_a[32-1:0] = memory_controller_alfabeto_out_struct_a[64-1:32];
		5: memory_controller_alfabeto_out_a[16-1:0] = memory_controller_alfabeto_out_struct_a[56-1:40];
		6: memory_controller_alfabeto_out_a[16-1:0] = memory_controller_alfabeto_out_struct_a[64-1:48];
		7: memory_controller_alfabeto_out_a[8-1:0] = memory_controller_alfabeto_out_struct_a[64-1:56];
	endcase

	memory_controller_intermediarios_out_a = 0;
	case(prevAddr_a)
		0: memory_controller_intermediarios_out_a[64-1:0] = memory_controller_intermediarios_out_struct_a[64-1:0];
		1: memory_controller_intermediarios_out_a[32-1:0] = memory_controller_intermediarios_out_struct_a[40-1:8];
		2: memory_controller_intermediarios_out_a[32-1:0] = memory_controller_intermediarios_out_struct_a[48-1:16];
		3: memory_controller_intermediarios_out_a[32-1:0] = memory_controller_intermediarios_out_struct_a[56-1:24];
		4: memory_controller_intermediarios_out_a[32-1:0] = memory_controller_intermediarios_out_struct_a[64-1:32];
		5: memory_controller_intermediarios_out_a[16-1:0] = memory_controller_intermediarios_out_struct_a[56-1:40];
		6: memory_controller_intermediarios_out_a[16-1:0] = memory_controller_intermediarios_out_struct_a[64-1:48];
		7: memory_controller_intermediarios_out_a[8-1:0] = memory_controller_intermediarios_out_struct_a[64-1:56];
	endcase

	memory_controller_out_prev_a = memory_controller_out_reg_a & { 64{!memory_controller_enable_reg_a}};
	memory_controller_out_a = 1'b0 | memory_controller_out_prev_a | memory_controller_texto_out_a | memory_controller_alfabeto_out_a | memory_controller_intermediarios_out_a | memory_controller_heap_out_a;
end

always @(posedge clk)
if (!memory_controller_waitrequest)
begin
memory_controller_out_reg_a <= memory_controller_out_a;
memory_controller_enable_reg_a <= memory_controller_enable_a;
end

always @(posedge clk)
if (!memory_controller_waitrequest)
for (j = 0; j < ram_latency; j=j+1)
begin
select_texto_reg_a[j+1] <= select_texto_reg_a[j];
select_alfabeto_reg_a[j+1] <= select_alfabeto_reg_a[j];
select_intermediarios_reg_a[j+1] <= select_intermediarios_reg_a[j];
select_heap_reg_a[j+1] <= select_heap_reg_a[j];
end
always @(*)
begin
select_texto_reg_a[0] <= select_texto_a;
select_alfabeto_reg_a[0] <= select_alfabeto_a;
select_intermediarios_reg_a[0] <= select_intermediarios_a;
select_heap_reg_a[0] <= select_heap_a;
end

reg [2:0] select_not_struct_b;

wire select_texto_b;
assign select_texto_b = (tag_b == `TAG_g_texto);
reg [ram_latency:0] select_texto_reg_b;
wire [7:0] memory_controller_texto_out_b;
assign memory_controller_texto_out_b = {8{ select_texto_reg_b[ram_latency]}} & texto_out_b;

wire select_alfabeto_b;
assign select_alfabeto_b = (tag_b == `TAG_g_alfabeto);
reg [ram_latency:0] select_alfabeto_reg_b;
reg [63:0] memory_controller_alfabeto_out_b;
wire [63:0] memory_controller_alfabeto_out_struct_b;
assign memory_controller_alfabeto_out_struct_b = {64{ select_alfabeto_reg_b[ram_latency]}} & alfabeto_out_b;

wire select_intermediarios_b;
assign select_intermediarios_b = (tag_b == `TAG_g_intermediarios);
reg [ram_latency:0] select_intermediarios_reg_b;
reg [63:0] memory_controller_intermediarios_out_b;
wire [63:0] memory_controller_intermediarios_out_struct_b;
assign memory_controller_intermediarios_out_struct_b = {64{ select_intermediarios_reg_b[ram_latency]}} & intermediarios_out_b;

wire select_heap_b;
assign select_heap_b = (tag_b == `TAG_g_heap);
reg [ram_latency:0] select_heap_reg_b;
wire [31:0] memory_controller_heap_out_b;
assign memory_controller_heap_out_b = {32{ select_heap_reg_b[ram_latency]}} & heap_out_b;

always @(*)
begin
	texto_address_b = memory_controller_address_b [10-1+0:0] & {10{select_texto_b}};
	texto_write_enable_b = memory_controller_write_enable_b & select_texto_b;
	texto_in_b [8-1:0] = memory_controller_in_b[8-1:0];

	alfabeto_address_b = memory_controller_address_b[11-1:3] & {8{select_alfabeto_b}};
	alfabeto_write_enable_b = memory_controller_write_enable_b & select_alfabeto_b;
				alfabeto_in_b = 0;
		case(memory_controller_size_b)
			3:
			begin
				alfabeto_in_b[64-1:0] = memory_controller_in_b[64-1:0];
				alfabeto_byteena_b = 8'b11111111;
			end
			2:
			begin
				if (memory_controller_address_b [2:2] == 0)
				begin
					alfabeto_in_b[32-1:0] = memory_controller_in_b[32-1:0];
					alfabeto_byteena_b = 8'b00001111;
				end
				else
				begin
					alfabeto_in_b[64-1:32] = memory_controller_in_b[32-1:0];
					alfabeto_byteena_b = 8'b11110000;
				end
			end
			1:
			begin
				case (memory_controller_address_b[2:1])
					0:
					begin
						alfabeto_in_b[16-1:0] = memory_controller_in_b[16-1:0];
						alfabeto_byteena_b = 8'd3;
					end
					1:
					begin
						alfabeto_in_b[32-1:16] = memory_controller_in_b[16-1:0];
						alfabeto_byteena_b = 8'd12;
					end
					2:
					begin
						alfabeto_in_b[48-1:32] = memory_controller_in_b[16-1:0];
						alfabeto_byteena_b = 8'd48;
					end
					3:
					begin
						alfabeto_in_b[64-1:48] = memory_controller_in_b[16-1:0];
						alfabeto_byteena_b = 8'd192;
					end
				endcase
			end
			0:
				case (memory_controller_address_b[2:0])
					0:
					begin
						alfabeto_in_b[8-1:0] = memory_controller_in_b[8-1:0];
						alfabeto_byteena_b = 8'd1;
					end
					1:
					begin
						alfabeto_in_b[16-1:8] = memory_controller_in_b[8-1:0];
						alfabeto_byteena_b = 8'd2;
					end
					2:
					begin
						alfabeto_in_b[24-1:16] = memory_controller_in_b[8-1:0];
						alfabeto_byteena_b = 8'd4;
					end
					3:
					begin
						alfabeto_in_b[32-1:24] = memory_controller_in_b[8-1:0];
						alfabeto_byteena_b = 8'd8;
					end
					4:
					begin
						alfabeto_in_b[40-1:32] = memory_controller_in_b[8-1:0];
						alfabeto_byteena_b = 8'd16;
					end
					5:
					begin
						alfabeto_in_b[48-1:40] = memory_controller_in_b[8-1:0];
						alfabeto_byteena_b = 8'd32;
					end
					6:
					begin
						alfabeto_in_b[56-1:48] = memory_controller_in_b[8-1:0];
						alfabeto_byteena_b = 8'd64;
					end
					7:
					begin
						alfabeto_in_b[64-1:56] = memory_controller_in_b[8-1:0];
						alfabeto_byteena_b = 8'd128;
					end
			endcase
		endcase

	intermediarios_address_b = memory_controller_address_b[11-1:3] & {8{select_intermediarios_b}};
	intermediarios_write_enable_b = memory_controller_write_enable_b & select_intermediarios_b;
				intermediarios_in_b = 0;
		case(memory_controller_size_b)
			3:
			begin
				intermediarios_in_b[64-1:0] = memory_controller_in_b[64-1:0];
				intermediarios_byteena_b = 8'b11111111;
			end
			2:
			begin
				if (memory_controller_address_b [2:2] == 0)
				begin
					intermediarios_in_b[32-1:0] = memory_controller_in_b[32-1:0];
					intermediarios_byteena_b = 8'b00001111;
				end
				else
				begin
					intermediarios_in_b[64-1:32] = memory_controller_in_b[32-1:0];
					intermediarios_byteena_b = 8'b11110000;
				end
			end
			1:
			begin
				case (memory_controller_address_b[2:1])
					0:
					begin
						intermediarios_in_b[16-1:0] = memory_controller_in_b[16-1:0];
						intermediarios_byteena_b = 8'd3;
					end
					1:
					begin
						intermediarios_in_b[32-1:16] = memory_controller_in_b[16-1:0];
						intermediarios_byteena_b = 8'd12;
					end
					2:
					begin
						intermediarios_in_b[48-1:32] = memory_controller_in_b[16-1:0];
						intermediarios_byteena_b = 8'd48;
					end
					3:
					begin
						intermediarios_in_b[64-1:48] = memory_controller_in_b[16-1:0];
						intermediarios_byteena_b = 8'd192;
					end
				endcase
			end
			0:
				case (memory_controller_address_b[2:0])
					0:
					begin
						intermediarios_in_b[8-1:0] = memory_controller_in_b[8-1:0];
						intermediarios_byteena_b = 8'd1;
					end
					1:
					begin
						intermediarios_in_b[16-1:8] = memory_controller_in_b[8-1:0];
						intermediarios_byteena_b = 8'd2;
					end
					2:
					begin
						intermediarios_in_b[24-1:16] = memory_controller_in_b[8-1:0];
						intermediarios_byteena_b = 8'd4;
					end
					3:
					begin
						intermediarios_in_b[32-1:24] = memory_controller_in_b[8-1:0];
						intermediarios_byteena_b = 8'd8;
					end
					4:
					begin
						intermediarios_in_b[40-1:32] = memory_controller_in_b[8-1:0];
						intermediarios_byteena_b = 8'd16;
					end
					5:
					begin
						intermediarios_in_b[48-1:40] = memory_controller_in_b[8-1:0];
						intermediarios_byteena_b = 8'd32;
					end
					6:
					begin
						intermediarios_in_b[56-1:48] = memory_controller_in_b[8-1:0];
						intermediarios_byteena_b = 8'd64;
					end
					7:
					begin
						intermediarios_in_b[64-1:56] = memory_controller_in_b[8-1:0];
						intermediarios_byteena_b = 8'd128;
					end
			endcase
		endcase

	heap_address_b = memory_controller_address_b [8-1+2:2] & {8{select_heap_b}};
	heap_write_enable_b = memory_controller_write_enable_b & select_heap_b;
	heap_in_b [32-1:0] = memory_controller_in_b[32-1:0];

end
always @(*)
begin
	select_not_struct_b [2:0] = 3'b0 | {2{select_heap_reg_b[ram_latency]}};
	if (prevAddr_b[2:0] & select_not_struct_b[2:0] != 0 && memory_controller_enable_b)
	begin
		$display("Error: memory address not aligned to ram word size!");
		$finish;
	end

	prevSize_b_and[0] = prevSize_b[1] | prevSize_b[0];
	prevSize_b_and[1] = prevSize_b[1];
	prevSize_b_and[2] = prevSize_b[1] & prevSize_b[0];
	if ((prevAddr_b & prevSize_b_and) != 0 && memory_controller_enable_b)
	begin
		$display("Error: memory address not aligned to ram word size!");
		$finish;
	end
	memory_controller_alfabeto_out_b = 0;
	case(prevAddr_b)
		0: memory_controller_alfabeto_out_b[64-1:0] = memory_controller_alfabeto_out_struct_b[64-1:0];
		1: memory_controller_alfabeto_out_b[32-1:0] = memory_controller_alfabeto_out_struct_b[40-1:8];
		2: memory_controller_alfabeto_out_b[32-1:0] = memory_controller_alfabeto_out_struct_b[48-1:16];
		3: memory_controller_alfabeto_out_b[32-1:0] = memory_controller_alfabeto_out_struct_b[56-1:24];
		4: memory_controller_alfabeto_out_b[32-1:0] = memory_controller_alfabeto_out_struct_b[64-1:32];
		5: memory_controller_alfabeto_out_b[16-1:0] = memory_controller_alfabeto_out_struct_b[56-1:40];
		6: memory_controller_alfabeto_out_b[16-1:0] = memory_controller_alfabeto_out_struct_b[64-1:48];
		7: memory_controller_alfabeto_out_b[8-1:0] = memory_controller_alfabeto_out_struct_b[64-1:56];
	endcase

	memory_controller_intermediarios_out_b = 0;
	case(prevAddr_b)
		0: memory_controller_intermediarios_out_b[64-1:0] = memory_controller_intermediarios_out_struct_b[64-1:0];
		1: memory_controller_intermediarios_out_b[32-1:0] = memory_controller_intermediarios_out_struct_b[40-1:8];
		2: memory_controller_intermediarios_out_b[32-1:0] = memory_controller_intermediarios_out_struct_b[48-1:16];
		3: memory_controller_intermediarios_out_b[32-1:0] = memory_controller_intermediarios_out_struct_b[56-1:24];
		4: memory_controller_intermediarios_out_b[32-1:0] = memory_controller_intermediarios_out_struct_b[64-1:32];
		5: memory_controller_intermediarios_out_b[16-1:0] = memory_controller_intermediarios_out_struct_b[56-1:40];
		6: memory_controller_intermediarios_out_b[16-1:0] = memory_controller_intermediarios_out_struct_b[64-1:48];
		7: memory_controller_intermediarios_out_b[8-1:0] = memory_controller_intermediarios_out_struct_b[64-1:56];
	endcase

	memory_controller_out_prev_b = memory_controller_out_reg_b & { 64{!memory_controller_enable_reg_b}};
	memory_controller_out_b = 1'b0 | memory_controller_out_prev_b | memory_controller_texto_out_b | memory_controller_alfabeto_out_b | memory_controller_intermediarios_out_b | memory_controller_heap_out_b;
end

always @(posedge clk)
if (!memory_controller_waitrequest)
begin
memory_controller_out_reg_b <= memory_controller_out_b;
memory_controller_enable_reg_b <= memory_controller_enable_b;
end

always @(posedge clk)
if (!memory_controller_waitrequest)
for (j = 0; j < ram_latency; j=j+1)
begin
select_texto_reg_b[j+1] <= select_texto_reg_b[j];
select_alfabeto_reg_b[j+1] <= select_alfabeto_reg_b[j];
select_intermediarios_reg_b[j+1] <= select_intermediarios_reg_b[j];
select_heap_reg_b[j+1] <= select_heap_reg_b[j];
end
always @(*)
begin
select_texto_reg_b[0] <= select_texto_b;
select_alfabeto_reg_b[0] <= select_alfabeto_b;
select_intermediarios_reg_b[0] <= select_intermediarios_b;
select_heap_reg_b[0] <= select_heap_b;
end

endmodule 

`timescale 1 ns / 1 ns
module main
(
	clk,
	clk2x,
	clk1x_follower,
	reset,
	start,
	finish,
	memory_controller_waitrequest,
	memory_controller_enable_a,
	memory_controller_address_a,
	memory_controller_write_enable_a,
	memory_controller_in_a,
	memory_controller_size_a,
	memory_controller_out_a,
	memory_controller_enable_b,
	memory_controller_address_b,
	memory_controller_write_enable_b,
	memory_controller_in_b,
	memory_controller_size_b,
	memory_controller_out_b,
	return_val,
	arg_argc,
	arg_argv
);

parameter [7:0] LEGUP_0 = 8'd0;
parameter [7:0] LEGUP_F_main_BB__1_1 = 8'd1;
parameter [7:0] LEGUP_F_main_BB__1_2 = 8'd2;
parameter [7:0] LEGUP_F_main_BB__1_3 = 8'd3;
parameter [7:0] LEGUP_F_main_BB__4_4 = 8'd4;
parameter [7:0] LEGUP_F_main_BB__6_5 = 8'd5;
parameter [7:0] LEGUP_F_main_BB__6_6 = 8'd6;
parameter [7:0] LEGUP_F_main_BB__6_7 = 8'd7;
parameter [7:0] LEGUP_F_main_BB__6_8 = 8'd8;
parameter [7:0] LEGUP_F_main_BB__6_9 = 8'd9;
parameter [7:0] LEGUP_F_main_BB__6_10 = 8'd10;
parameter [7:0] LEGUP_F_main_BB_count_frequenciesexitpreheaderpreheader_11 = 8'd11;
parameter [7:0] LEGUP_F_main_BB_count_frequenciesexitpreheader_12 = 8'd12;
parameter [7:0] LEGUP_F_main_BB_count_frequenciesexitpreheader_13 = 8'd13;
parameter [7:0] LEGUP_F_main_BB_count_frequenciesexitpreheader_14 = 8'd14;
parameter [7:0] LEGUP_F_main_BB__15_15 = 8'd15;
parameter [7:0] LEGUP_F_main_BB__17_16 = 8'd16;
parameter [7:0] LEGUP_F_main_BB__19_17 = 8'd17;
parameter [7:0] LEGUP_F_main_BB__19_18 = 8'd18;
parameter [7:0] LEGUP_F_main_BB__19_19 = 8'd19;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_20 = 8'd20;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_21 = 8'd21;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_22 = 8'd22;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_23 = 8'd23;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_24 = 8'd24;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_25 = 8'd25;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_26 = 8'd26;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_27 = 8'd27;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_28 = 8'd28;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_29 = 8'd29;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_30 = 8'd30;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_31 = 8'd31;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_32 = 8'd32;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_33 = 8'd33;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_34 = 8'd34;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_35 = 8'd35;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_36 = 8'd36;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_37 = 8'd37;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_38 = 8'd38;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_39 = 8'd39;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_40 = 8'd40;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_41 = 8'd41;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_42 = 8'd42;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_43 = 8'd43;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_44 = 8'd44;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_45 = 8'd45;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_46 = 8'd46;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_47 = 8'd47;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_48 = 8'd48;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_49 = 8'd49;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_50 = 8'd50;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_51 = 8'd51;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_52 = 8'd52;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_53 = 8'd53;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_54 = 8'd54;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_55 = 8'd55;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader_56 = 8'd56;
parameter [7:0] LEGUP_F_main_BB_lrphpreheader_57 = 8'd57;
parameter [7:0] LEGUP_F_main_BB_lrph_58 = 8'd58;
parameter [7:0] LEGUP_F_main_BB_lrph_59 = 8'd59;
parameter [7:0] LEGUP_F_main_BB_lrph_60 = 8'd60;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_61 = 8'd61;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_62 = 8'd62;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_63 = 8'd63;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_64 = 8'd64;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_65 = 8'd65;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_66 = 8'd66;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_67 = 8'd67;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_68 = 8'd68;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_69 = 8'd69;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_70 = 8'd70;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_71 = 8'd71;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_72 = 8'd72;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_73 = 8'd73;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_74 = 8'd74;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_75 = 8'd75;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_76 = 8'd76;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_77 = 8'd77;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_78 = 8'd78;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_79 = 8'd79;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_80 = 8'd80;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_81 = 8'd81;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_82 = 8'd82;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_83 = 8'd83;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_84 = 8'd84;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_85 = 8'd85;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_86 = 8'd86;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_87 = 8'd87;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_88 = 8'd88;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_89 = 8'd89;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_90 = 8'd90;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_91 = 8'd91;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_92 = 8'd92;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_93 = 8'd93;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_94 = 8'd94;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_95 = 8'd95;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_96 = 8'd96;
parameter [7:0] LEGUP_F_main_BB__crit_edgei_97 = 8'd97;
parameter [7:0] LEGUP_F_main_BB_insertexitloopexit_98 = 8'd98;
parameter [7:0] LEGUP_F_main_BB_insertexit_99 = 8'd99;
parameter [7:0] LEGUP_F_main_BB__44_100 = 8'd100;
parameter [7:0] LEGUP_F_main_BB_lrph14ipreheader_101 = 8'd101;
parameter [7:0] LEGUP_F_main_BB_lrph14i_102 = 8'd102;
parameter [7:0] LEGUP_F_main_BB_lrph14i_103 = 8'd103;
parameter [7:0] LEGUP_F_main_BB_lrph14i_104 = 8'd104;
parameter [7:0] LEGUP_F_main_BB_lrph14i_105 = 8'd105;
parameter [7:0] LEGUP_F_main_BB_lrph14i_106 = 8'd106;
parameter [7:0] LEGUP_F_main_BB_lrphiiipreheader_107 = 8'd107;
parameter [7:0] LEGUP_F_main_BB_lrphiii_108 = 8'd108;
parameter [7:0] LEGUP_F_main_BB__56_109 = 8'd109;
parameter [7:0] LEGUP_F_main_BB__56_110 = 8'd110;
parameter [7:0] LEGUP_F_main_BB__56_111 = 8'd111;
parameter [7:0] LEGUP_F_main_BB__56_112 = 8'd112;
parameter [7:0] LEGUP_F_main_BB__56_113 = 8'd113;
parameter [7:0] LEGUP_F_main_BB__67_114 = 8'd114;
parameter [7:0] LEGUP_F_main_BB__67_115 = 8'd115;
parameter [7:0] LEGUP_F_main_BB__67_116 = 8'd116;
parameter [7:0] LEGUP_F_main_BB__67_117 = 8'd117;
parameter [7:0] LEGUP_F_main_BB__67_118 = 8'd118;
parameter [7:0] LEGUP_F_main_BB__77_119 = 8'd119;
parameter [7:0] LEGUP_F_main_BB__77_120 = 8'd120;
parameter [7:0] LEGUP_F_main_BB__77_121 = 8'd121;
parameter [7:0] LEGUP_F_main_BB_get_minexitiloopexit_122 = 8'd122;
parameter [7:0] LEGUP_F_main_BB_get_minexiti_123 = 8'd123;
parameter [7:0] LEGUP_F_main_BB_get_minexiti_124 = 8'd124;
parameter [7:0] LEGUP_F_main_BB_get_minexiti_125 = 8'd125;
parameter [7:0] LEGUP_F_main_BB_get_minexiti_126 = 8'd126;
parameter [7:0] LEGUP_F_main_BB_get_minexiti_127 = 8'd127;
parameter [7:0] LEGUP_F_main_BB_lrphii9ipreheader_128 = 8'd128;
parameter [7:0] LEGUP_F_main_BB_lrphii9i_129 = 8'd129;
parameter [7:0] LEGUP_F_main_BB__87_130 = 8'd130;
parameter [7:0] LEGUP_F_main_BB__87_131 = 8'd131;
parameter [7:0] LEGUP_F_main_BB__87_132 = 8'd132;
parameter [7:0] LEGUP_F_main_BB__87_133 = 8'd133;
parameter [7:0] LEGUP_F_main_BB__87_134 = 8'd134;
parameter [7:0] LEGUP_F_main_BB__98_135 = 8'd135;
parameter [7:0] LEGUP_F_main_BB__98_136 = 8'd136;
parameter [7:0] LEGUP_F_main_BB__98_137 = 8'd137;
parameter [7:0] LEGUP_F_main_BB__98_138 = 8'd138;
parameter [7:0] LEGUP_F_main_BB__98_139 = 8'd139;
parameter [7:0] LEGUP_F_main_BB__108_140 = 8'd140;
parameter [7:0] LEGUP_F_main_BB__108_141 = 8'd141;
parameter [7:0] LEGUP_F_main_BB__108_142 = 8'd142;
parameter [7:0] LEGUP_F_main_BB_get_minexit12iloopexit_143 = 8'd143;
parameter [7:0] LEGUP_F_main_BB_get_minexit12i_144 = 8'd144;
parameter [7:0] LEGUP_F_main_BB_get_minexit12i_145 = 8'd145;
parameter [7:0] LEGUP_F_main_BB_get_minexit12i_146 = 8'd146;
parameter [7:0] LEGUP_F_main_BB_get_minexit12i_147 = 8'd147;
parameter [7:0] LEGUP_F_main_BB_get_minexit12i_148 = 8'd148;
parameter [7:0] LEGUP_F_main_BB_insertexitithread_149 = 8'd149;
parameter [7:0] LEGUP_F_main_BB_lrph14ibackedge_150 = 8'd150;
parameter [7:0] LEGUP_F_main_BB__120_151 = 8'd151;
parameter [7:0] LEGUP_F_main_BB__120_152 = 8'd152;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_153 = 8'd153;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_154 = 8'd154;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_155 = 8'd155;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_156 = 8'd156;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_157 = 8'd157;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_158 = 8'd158;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_159 = 8'd159;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_160 = 8'd160;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_161 = 8'd161;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_162 = 8'd162;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_163 = 8'd163;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_164 = 8'd164;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_165 = 8'd165;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_166 = 8'd166;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_167 = 8'd167;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_168 = 8'd168;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_169 = 8'd169;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_170 = 8'd170;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_171 = 8'd171;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_172 = 8'd172;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_173 = 8'd173;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_174 = 8'd174;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_175 = 8'd175;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_176 = 8'd176;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_177 = 8'd177;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_178 = 8'd178;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_179 = 8'd179;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_180 = 8'd180;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_181 = 8'd181;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_182 = 8'd182;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_183 = 8'd183;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_184 = 8'd184;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_185 = 8'd185;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_186 = 8'd186;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_187 = 8'd187;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_188 = 8'd188;
parameter [7:0] LEGUP_F_main_BB_lrphipreheaderi_189 = 8'd189;
parameter [7:0] LEGUP_F_main_BB_lrphipreheader1_190 = 8'd190;
parameter [7:0] LEGUP_F_main_BB_lrphi_191 = 8'd191;
parameter [7:0] LEGUP_F_main_BB_lrphi_192 = 8'd192;
parameter [7:0] LEGUP_F_main_BB_lrphi_193 = 8'd193;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_194 = 8'd194;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_195 = 8'd195;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_196 = 8'd196;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_197 = 8'd197;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_198 = 8'd198;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_199 = 8'd199;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_200 = 8'd200;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_201 = 8'd201;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_202 = 8'd202;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_203 = 8'd203;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_204 = 8'd204;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_205 = 8'd205;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_206 = 8'd206;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_207 = 8'd207;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_208 = 8'd208;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_209 = 8'd209;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_210 = 8'd210;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_211 = 8'd211;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_212 = 8'd212;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_213 = 8'd213;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_214 = 8'd214;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_215 = 8'd215;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_216 = 8'd216;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_217 = 8'd217;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_218 = 8'd218;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_219 = 8'd219;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_220 = 8'd220;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_221 = 8'd221;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_222 = 8'd222;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_223 = 8'd223;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_224 = 8'd224;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_225 = 8'd225;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_226 = 8'd226;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_227 = 8'd227;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_228 = 8'd228;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_229 = 8'd229;
parameter [7:0] LEGUP_F_main_BB__crit_edgeii_230 = 8'd230;
parameter [7:0] LEGUP_F_main_BB_insertexitiloopexit_231 = 8'd231;
parameter [7:0] LEGUP_F_main_BB_insertexiti_232 = 8'd232;
parameter [7:0] LEGUP_F_main_BB_build_trieexitloopexit_233 = 8'd233;
parameter [7:0] LEGUP_F_main_BB_build_trieexit_234 = 8'd234;
parameter [7:0] LEGUP_F_main_BB_build_trieexit_235 = 8'd235;
parameter [7:0] LEGUP_F_main_BB_build_trieexit_236 = 8'd236;
parameter [7:0] LEGUP_F_main_BB_build_trieexit_237 = 8'd237;
parameter [7:0] LEGUP_F_main_BB_build_trieexit_238 = 8'd238;
parameter [8:0] tag_offset = 9'd0;
parameter [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] tag_addr_offset = {tag_offset, 23'd0};

input  clk;
input  clk2x;
input  clk1x_follower;
input  reset;
input  start;
output reg  finish;
input  memory_controller_waitrequest;
output reg  memory_controller_enable_a;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_a;
output reg  memory_controller_write_enable_a;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in_a;
output reg [1:0] memory_controller_size_a;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out_a;
output reg  memory_controller_enable_b;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_b;
output reg  memory_controller_write_enable_b;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in_b;
output reg [1:0] memory_controller_size_b;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out_b;
output reg [31:0] return_val;
input [31:0] arg_argc;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_argv;
reg [7:0] cur_state;
reg [7:0] next_state;
reg [31:0] main_1_i105;
reg [31:0] main_1_i105_reg;
reg [7:0] main_1_2;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_scevgep6;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_scevgep6_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_scevgep7;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_scevgep7_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_scevgep89;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_scevgep10;
reg [31:0] main_1_3;
reg [31:0] main_1_3_reg;
reg  main_1_exitcond5;
reg  main_1_exitcond5_reg;
reg [31:0] main_6_i102i;
reg [31:0] main_6_i102i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_6_scevgep4;
reg [7:0] main_6_7;
reg [31:0] main_6_8;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_6_9;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_6_9_reg;
reg [31:0] main_6_10;
reg [31:0] main_6_11;
reg [31:0] main_6_12;
reg [31:0] main_6_12_reg;
reg  main_6_exitcond;
reg  main_6_exitcond_reg;
reg [31:0] main_count_frequenciesexitpreheader_heap_size0;
reg [31:0] main_count_frequenciesexitpreheader_heap_size0_reg;
reg [31:0] main_count_frequenciesexitpreheader_i204;
reg [31:0] main_count_frequenciesexitpreheader_i204_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_count_frequenciesexitpreheader_scevgep;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_count_frequenciesexitpreheader_scevgep_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_count_frequenciesexitpreheader_scevgep3;
reg [31:0] main_count_frequenciesexitpreheader_13;
reg [31:0] main_count_frequenciesexitpreheader_13_reg;
reg  main_count_frequenciesexitpreheader_14;
reg  main_15_16;
reg [31:0] main_19_20;
reg [31:0] main_19_20_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_19_21;
reg  main_19_22;
reg  main_19_22_reg;
reg [31:0] main_lrphipreheader_23;
reg [31:0] main_lrphipreheader_23_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphipreheader_24;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphipreheader_24_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphipreheader_25;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphipreheader_25_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphipreheader_26;
reg [31:0] main_lrphipreheader_27;
reg  main_lrphipreheader_28;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph_29;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph_29_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph_30;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph_30_reg;
reg [31:0] main_lrph_31;
reg [31:0] main_lrph_31_reg;
reg [31:0] main_lrph_p01i3;
reg [31:0] main_lrph_p01i3_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph_32;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph_32_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph_33;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph_33_reg;
reg  main_lrph_34;
reg  main_lrph_34_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgei_prei;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgei_prei_reg;
reg [31:0] main__crit_edgei_35;
reg [31:0] main__crit_edgei_35_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgei_36;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgei_36_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgei_37;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgei_37_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgei_38;
reg [31:0] main__crit_edgei_39;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgei_40;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgei_40_reg;
reg [31:0] main__crit_edgei_41;
reg [31:0] main__crit_edgei_41_reg;
reg  main__crit_edgei_42;
reg [31:0] main_insertexit_heap_size1;
reg [31:0] main_insertexit_heap_size1_reg;
reg [31:0] main_insertexit_43;
reg  main_insertexit_exitcond2;
reg  main_44_47;
reg [31:0] main_lrph14i_used_intermediaries0;
reg [31:0] main_lrph14i_used_intermediaries0_reg;
reg [31:0] main_lrph14i_48;
reg [31:0] main_lrph14i_48_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph14i_49;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph14i_49_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph14i_50;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph14i_50_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph14i_51;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph14i_51_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrph14i_52;
reg [31:0] main_lrph14i_53;
reg [31:0] main_lrph14i_53_reg;
reg  main_lrph14i_54;
reg  main_lrph14i_54_reg;
reg [31:0] main_lrphiii_filho02iii;
reg [31:0] main_lrphiii_filho02iii_reg;
reg [31:0] main_lrphiii_pai01iii;
reg [31:0] main_lrphiii_pai01iii_reg;
reg  main_lrphiii_55;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_56_57;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_56_58;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_56_59;
reg [31:0] main_56_60;
reg [31:0] main_56_61;
reg [31:0] main_56_61_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_56_62;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_56_63;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_56_64;
reg [31:0] main_56_65;
reg  main_56_66;
reg [31:0] main_56_filho0iii;
reg [31:0] main_67_filho1iii;
reg [31:0] main_67_filho1iii_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_67_68;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_67_68_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_67_69;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_67_69_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_67_70;
reg [31:0] main_67_71;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_67_72;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_67_72_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_67_73;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_67_73_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_67_74;
reg [31:0] main_67_75;
reg  main_67_76;
reg [31:0] main_77_78;
reg [31:0] main_77_78_reg;
reg  main_77_79;
reg  main_77_79_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexiti_80;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexiti_80_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexiti_81;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexiti_81_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexiti_82;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexiti_82_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexiti_83;
reg [31:0] main_get_minexiti_84;
reg [31:0] main_get_minexiti_84_reg;
reg  main_get_minexiti_85;
reg  main_get_minexiti_85_reg;
reg [31:0] main_lrphii9i_filho02ii7i;
reg [31:0] main_lrphii9i_filho02ii7i_reg;
reg [31:0] main_lrphii9i_pai01ii8i;
reg [31:0] main_lrphii9i_pai01ii8i_reg;
reg  main_lrphii9i_86;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_87_88;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_87_89;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_87_90;
reg [31:0] main_87_91;
reg [31:0] main_87_92;
reg [31:0] main_87_92_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_87_93;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_87_94;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_87_95;
reg [31:0] main_87_96;
reg  main_87_97;
reg [31:0] main_87_filho0ii10i;
reg [31:0] main_98_filho1ii11i;
reg [31:0] main_98_filho1ii11i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_98_99;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_98_99_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_98_100;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_98_100_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_98_101;
reg [31:0] main_98_102;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_98_103;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_98_103_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_98_104;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_98_104_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_98_105;
reg [31:0] main_98_106;
reg  main_98_107;
reg [31:0] main_108_109;
reg [31:0] main_108_109_reg;
reg  main_108_110;
reg  main_108_110_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexit12i_111;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexit12i_112;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexit12i_112_reg;
reg [31:0] main_get_minexit12i_113;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexit12i_114;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexit12i_114_reg;
reg [31:0] main_get_minexit12i_115;
reg [31:0] main_get_minexit12i_116;
reg [31:0] main_get_minexit12i_116_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexit12i_117;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_minexit12i_117_reg;
reg  main_get_minexit12i_118;
reg  main_get_minexit12i_118_reg;
reg [31:0] main_lrph14ibackedge_be;
reg [31:0] main_lrph14ibackedge_be_reg;
reg [31:0] main_lrph14ibackedge_used_intermediaries0be;
reg  main_120_121;
reg  main_120_121_reg;
reg [31:0] main_lrphipreheaderi_122;
reg [31:0] main_lrphipreheaderi_122_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphipreheaderi_123;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphipreheaderi_123_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphipreheaderi_124;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphipreheaderi_124_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphipreheaderi_125;
reg [31:0] main_lrphipreheaderi_126;
reg  main_lrphipreheaderi_127;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphi_128;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphi_128_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphi_129;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphi_129_reg;
reg [31:0] main_lrphi_130;
reg [31:0] main_lrphi_130_reg;
reg [31:0] main_lrphi_p01i13i;
reg [31:0] main_lrphi_p01i13i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphi_131;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphi_131_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphi_132;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_lrphi_132_reg;
reg  main_lrphi_133;
reg  main_lrphi_133_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgeii_preii;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgeii_preii_reg;
reg [31:0] main__crit_edgeii_134;
reg [31:0] main__crit_edgeii_134_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgeii_135;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgeii_135_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgeii_136;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgeii_136_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgeii_137;
reg [31:0] main__crit_edgeii_138;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgeii_139;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__crit_edgeii_139_reg;
reg [31:0] main__crit_edgeii_140;
reg [31:0] main__crit_edgeii_140_reg;
reg  main__crit_edgeii_141;
reg  main_insertexiti_142;
reg [31:0] main_build_trieexit_lcssai;
reg [31:0] main_build_trieexit_lcssai_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_build_trieexit_143;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_build_trieexit_143_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_build_trieexit_144;
reg [31:0] main_signed_divide_32_0_op0;
reg [31:0] main_signed_divide_32_0_op1;
wire [31:0] lpm_divide_main_lrphipreheader_23_temp_out;
wire [31:0] main_lrphipreheader_23_unused;
reg  lpm_divide_main_lrphipreheader_23_en;
reg [31:0] lpm_divide_main_lrphipreheader_23_out;
reg [31:0] main_signed_divide_32_0;

/*   %23 = sdiv i32 %20, 2*/
lpm_divide lpm_divide_main_lrphipreheader_23 (
	.quotient (lpm_divide_main_lrphipreheader_23_temp_out),
	.remain (main_lrphipreheader_23_unused),
	.clock (clk),
	.aclr (1'd0),
	.clken (lpm_divide_main_lrphipreheader_23_en),
	.numer (main_signed_divide_32_0_op0),
	.denom (main_signed_divide_32_0_op1)
);

defparam
	lpm_divide_main_lrphipreheader_23.lpm_pipeline = 32,
	lpm_divide_main_lrphipreheader_23.lpm_widthn = 32,
	lpm_divide_main_lrphipreheader_23.lpm_widthd = 32,
	lpm_divide_main_lrphipreheader_23.lpm_drepresentation = "SIGNED",
	lpm_divide_main_lrphipreheader_23.lpm_nrepresentation = "SIGNED",
	lpm_divide_main_lrphipreheader_23.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE";


/* Unsynthesizable Statements */
always @(posedge clk)
	if (!memory_controller_waitrequest) begin
	/* main: %4*/
	/*   %5 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([40 x i8]* @.str, i32 0, i32 0)) #1*/
	if ((cur_state == LEGUP_F_main_BB__4_4)) begin
		$write("Calculando frequencia de caracteres...\n");
	end
	/* main: %17*/
	/*   %18 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str7, i32 0, i32 0)) #1*/
	if ((cur_state == LEGUP_F_main_BB__17_16)) begin
		$write("Heap cheio\n");
	end
	/* main: %44*/
	/*   %45 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([26 x i8]* @.str1, i32 0, i32 0)) #1*/
	if ((cur_state == LEGUP_F_main_BB__44_100)) begin
		$write("Calculo de frequencia OK\n");
	end
	/* main: %44*/
	/*   %46 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([19 x i8]* @.str2, i32 0, i32 0)) #1*/
	if ((cur_state == LEGUP_F_main_BB__44_100)) begin
		$write("Buildando trie...\n");
	end
	/* main: %insert.exit.i.thread*/
	/*   %119 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str7, i32 0, i32 0)) #1*/
	if ((cur_state == LEGUP_F_main_BB_insertexitithread_149)) begin
		$write("Heap cheio\n");
	end
	/* main: %build_trie.exit*/
	/*   %145 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str3, i32 0, i32 0)) #1*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_238)) begin
		$write("Build OK\n");
	end
	/* main: %build_trie.exit*/
	/*   %146 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([39 x i8]* @.str4, i32 0, i32 0)) #1*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_238)) begin
		$write("Printando codificação de Huffman...\n");
	end
	/* main: %build_trie.exit*/
	/*   %147 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([29 x i8]* @.str5, i32 0, i32 0)) #1*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_238)) begin
		$write("Codificação de Huffman OK\n");
	end
	/* main: %build_trie.exit*/
	/*   %148 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([18 x i8]* @.str6, i32 0, i32 0)) #1*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_238)) begin
		$write("\nFim do programa\n");
		led_huffman <= '1';
	end
end
always @(posedge clk) begin
if (reset == 1'b1)
	cur_state <= LEGUP_0;
else if (memory_controller_waitrequest == 1'd1)
	cur_state <= cur_state;
else
	cur_state <= next_state;
end

always @(*)
begin
next_state = cur_state;
case(cur_state)  // synthesis parallel_case  
LEGUP_0:
	if ((start == 1'd1))
		next_state = LEGUP_F_main_BB__1_1;
LEGUP_F_main_BB__108_140:
		next_state = LEGUP_F_main_BB__108_141;
LEGUP_F_main_BB__108_141:
		next_state = LEGUP_F_main_BB__108_142;
LEGUP_F_main_BB__108_142:
	if ((main_108_110_reg == 1'd1))
		next_state = LEGUP_F_main_BB_get_minexit12iloopexit_143;
	else if ((main_108_110_reg == 1'd0))
		next_state = LEGUP_F_main_BB_lrphii9i_129;
LEGUP_F_main_BB__120_151:
		next_state = LEGUP_F_main_BB__120_152;
LEGUP_F_main_BB__120_152:
	if ((main_120_121_reg == 1'd1))
		next_state = LEGUP_F_main_BB_lrphipreheaderi_153;
	else if ((main_120_121_reg == 1'd0))
		next_state = LEGUP_F_main_BB_insertexiti_232;
LEGUP_F_main_BB__15_15:
	if ((main_15_16 == 1'd1))
		next_state = LEGUP_F_main_BB__17_16;
	else if ((main_15_16 == 1'd0))
		next_state = LEGUP_F_main_BB__19_17;
LEGUP_F_main_BB__17_16:
		next_state = LEGUP_F_main_BB_insertexit_99;
LEGUP_F_main_BB__19_17:
		next_state = LEGUP_F_main_BB__19_18;
LEGUP_F_main_BB__19_18:
		next_state = LEGUP_F_main_BB__19_19;
LEGUP_F_main_BB__19_19:
	if ((main_19_22_reg == 1'd1))
		next_state = LEGUP_F_main_BB_lrphipreheader_20;
	else if ((main_19_22_reg == 1'd0))
		next_state = LEGUP_F_main_BB_insertexit_99;
LEGUP_F_main_BB__1_1:
		next_state = LEGUP_F_main_BB__1_2;
LEGUP_F_main_BB__1_2:
		next_state = LEGUP_F_main_BB__1_3;
LEGUP_F_main_BB__1_3:
	if ((main_1_exitcond5_reg == 1'd1))
		next_state = LEGUP_F_main_BB__4_4;
	else if ((main_1_exitcond5_reg == 1'd0))
		next_state = LEGUP_F_main_BB__1_1;
LEGUP_F_main_BB__44_100:
	if ((main_44_47 == 1'd1))
		next_state = LEGUP_F_main_BB_lrph14ipreheader_101;
	else if ((main_44_47 == 1'd0))
		next_state = LEGUP_F_main_BB_build_trieexit_234;
LEGUP_F_main_BB__4_4:
		next_state = LEGUP_F_main_BB__6_5;
LEGUP_F_main_BB__56_109:
		next_state = LEGUP_F_main_BB__56_110;
LEGUP_F_main_BB__56_110:
		next_state = LEGUP_F_main_BB__56_111;
LEGUP_F_main_BB__56_111:
		next_state = LEGUP_F_main_BB__56_112;
LEGUP_F_main_BB__56_112:
		next_state = LEGUP_F_main_BB__56_113;
LEGUP_F_main_BB__56_113:
		next_state = LEGUP_F_main_BB__67_114;
LEGUP_F_main_BB__67_114:
		next_state = LEGUP_F_main_BB__67_115;
LEGUP_F_main_BB__67_115:
		next_state = LEGUP_F_main_BB__67_116;
LEGUP_F_main_BB__67_116:
		next_state = LEGUP_F_main_BB__67_117;
LEGUP_F_main_BB__67_117:
		next_state = LEGUP_F_main_BB__67_118;
LEGUP_F_main_BB__67_118:
	if ((main_67_76 == 1'd1))
		next_state = LEGUP_F_main_BB__77_119;
	else if ((main_67_76 == 1'd0))
		next_state = LEGUP_F_main_BB_get_minexitiloopexit_122;
LEGUP_F_main_BB__6_10:
	if ((main_6_exitcond_reg == 1'd1))
		next_state = LEGUP_F_main_BB_count_frequenciesexitpreheaderpreheader_11;
	else if ((main_6_exitcond_reg == 1'd0))
		next_state = LEGUP_F_main_BB__6_5;
LEGUP_F_main_BB__6_5:
		next_state = LEGUP_F_main_BB__6_6;
LEGUP_F_main_BB__6_6:
		next_state = LEGUP_F_main_BB__6_7;
LEGUP_F_main_BB__6_7:
		next_state = LEGUP_F_main_BB__6_8;
LEGUP_F_main_BB__6_8:
		next_state = LEGUP_F_main_BB__6_9;
LEGUP_F_main_BB__6_9:
		next_state = LEGUP_F_main_BB__6_10;
LEGUP_F_main_BB__77_119:
		next_state = LEGUP_F_main_BB__77_120;
LEGUP_F_main_BB__77_120:
		next_state = LEGUP_F_main_BB__77_121;
LEGUP_F_main_BB__77_121:
	if ((main_77_79_reg == 1'd1))
		next_state = LEGUP_F_main_BB_get_minexitiloopexit_122;
	else if ((main_77_79_reg == 1'd0))
		next_state = LEGUP_F_main_BB_lrphiii_108;
LEGUP_F_main_BB__87_130:
		next_state = LEGUP_F_main_BB__87_131;
LEGUP_F_main_BB__87_131:
		next_state = LEGUP_F_main_BB__87_132;
LEGUP_F_main_BB__87_132:
		next_state = LEGUP_F_main_BB__87_133;
LEGUP_F_main_BB__87_133:
		next_state = LEGUP_F_main_BB__87_134;
LEGUP_F_main_BB__87_134:
		next_state = LEGUP_F_main_BB__98_135;
LEGUP_F_main_BB__98_135:
		next_state = LEGUP_F_main_BB__98_136;
LEGUP_F_main_BB__98_136:
		next_state = LEGUP_F_main_BB__98_137;
LEGUP_F_main_BB__98_137:
		next_state = LEGUP_F_main_BB__98_138;
LEGUP_F_main_BB__98_138:
		next_state = LEGUP_F_main_BB__98_139;
LEGUP_F_main_BB__98_139:
	if ((main_98_107 == 1'd1))
		next_state = LEGUP_F_main_BB__108_140;
	else if ((main_98_107 == 1'd0))
		next_state = LEGUP_F_main_BB_get_minexit12iloopexit_143;
LEGUP_F_main_BB__crit_edgei_61:
		next_state = LEGUP_F_main_BB__crit_edgei_62;
LEGUP_F_main_BB__crit_edgei_62:
		next_state = LEGUP_F_main_BB__crit_edgei_63;
LEGUP_F_main_BB__crit_edgei_63:
		next_state = LEGUP_F_main_BB__crit_edgei_64;
LEGUP_F_main_BB__crit_edgei_64:
		next_state = LEGUP_F_main_BB__crit_edgei_65;
LEGUP_F_main_BB__crit_edgei_65:
		next_state = LEGUP_F_main_BB__crit_edgei_66;
LEGUP_F_main_BB__crit_edgei_66:
		next_state = LEGUP_F_main_BB__crit_edgei_67;
LEGUP_F_main_BB__crit_edgei_67:
		next_state = LEGUP_F_main_BB__crit_edgei_68;
LEGUP_F_main_BB__crit_edgei_68:
		next_state = LEGUP_F_main_BB__crit_edgei_69;
LEGUP_F_main_BB__crit_edgei_69:
		next_state = LEGUP_F_main_BB__crit_edgei_70;
LEGUP_F_main_BB__crit_edgei_70:
		next_state = LEGUP_F_main_BB__crit_edgei_71;
LEGUP_F_main_BB__crit_edgei_71:
		next_state = LEGUP_F_main_BB__crit_edgei_72;
LEGUP_F_main_BB__crit_edgei_72:
		next_state = LEGUP_F_main_BB__crit_edgei_73;
LEGUP_F_main_BB__crit_edgei_73:
		next_state = LEGUP_F_main_BB__crit_edgei_74;
LEGUP_F_main_BB__crit_edgei_74:
		next_state = LEGUP_F_main_BB__crit_edgei_75;
LEGUP_F_main_BB__crit_edgei_75:
		next_state = LEGUP_F_main_BB__crit_edgei_76;
LEGUP_F_main_BB__crit_edgei_76:
		next_state = LEGUP_F_main_BB__crit_edgei_77;
LEGUP_F_main_BB__crit_edgei_77:
		next_state = LEGUP_F_main_BB__crit_edgei_78;
LEGUP_F_main_BB__crit_edgei_78:
		next_state = LEGUP_F_main_BB__crit_edgei_79;
LEGUP_F_main_BB__crit_edgei_79:
		next_state = LEGUP_F_main_BB__crit_edgei_80;
LEGUP_F_main_BB__crit_edgei_80:
		next_state = LEGUP_F_main_BB__crit_edgei_81;
LEGUP_F_main_BB__crit_edgei_81:
		next_state = LEGUP_F_main_BB__crit_edgei_82;
LEGUP_F_main_BB__crit_edgei_82:
		next_state = LEGUP_F_main_BB__crit_edgei_83;
LEGUP_F_main_BB__crit_edgei_83:
		next_state = LEGUP_F_main_BB__crit_edgei_84;
LEGUP_F_main_BB__crit_edgei_84:
		next_state = LEGUP_F_main_BB__crit_edgei_85;
LEGUP_F_main_BB__crit_edgei_85:
		next_state = LEGUP_F_main_BB__crit_edgei_86;
LEGUP_F_main_BB__crit_edgei_86:
		next_state = LEGUP_F_main_BB__crit_edgei_87;
LEGUP_F_main_BB__crit_edgei_87:
		next_state = LEGUP_F_main_BB__crit_edgei_88;
LEGUP_F_main_BB__crit_edgei_88:
		next_state = LEGUP_F_main_BB__crit_edgei_89;
LEGUP_F_main_BB__crit_edgei_89:
		next_state = LEGUP_F_main_BB__crit_edgei_90;
LEGUP_F_main_BB__crit_edgei_90:
		next_state = LEGUP_F_main_BB__crit_edgei_91;
LEGUP_F_main_BB__crit_edgei_91:
		next_state = LEGUP_F_main_BB__crit_edgei_92;
LEGUP_F_main_BB__crit_edgei_92:
		next_state = LEGUP_F_main_BB__crit_edgei_93;
LEGUP_F_main_BB__crit_edgei_93:
		next_state = LEGUP_F_main_BB__crit_edgei_94;
LEGUP_F_main_BB__crit_edgei_94:
		next_state = LEGUP_F_main_BB__crit_edgei_95;
LEGUP_F_main_BB__crit_edgei_95:
		next_state = LEGUP_F_main_BB__crit_edgei_96;
LEGUP_F_main_BB__crit_edgei_96:
		next_state = LEGUP_F_main_BB__crit_edgei_97;
LEGUP_F_main_BB__crit_edgei_97:
	if ((main__crit_edgei_42 == 1'd1))
		next_state = LEGUP_F_main_BB_lrph_58;
	else if ((main__crit_edgei_42 == 1'd0))
		next_state = LEGUP_F_main_BB_insertexitloopexit_98;
LEGUP_F_main_BB__crit_edgeii_194:
		next_state = LEGUP_F_main_BB__crit_edgeii_195;
LEGUP_F_main_BB__crit_edgeii_195:
		next_state = LEGUP_F_main_BB__crit_edgeii_196;
LEGUP_F_main_BB__crit_edgeii_196:
		next_state = LEGUP_F_main_BB__crit_edgeii_197;
LEGUP_F_main_BB__crit_edgeii_197:
		next_state = LEGUP_F_main_BB__crit_edgeii_198;
LEGUP_F_main_BB__crit_edgeii_198:
		next_state = LEGUP_F_main_BB__crit_edgeii_199;
LEGUP_F_main_BB__crit_edgeii_199:
		next_state = LEGUP_F_main_BB__crit_edgeii_200;
LEGUP_F_main_BB__crit_edgeii_200:
		next_state = LEGUP_F_main_BB__crit_edgeii_201;
LEGUP_F_main_BB__crit_edgeii_201:
		next_state = LEGUP_F_main_BB__crit_edgeii_202;
LEGUP_F_main_BB__crit_edgeii_202:
		next_state = LEGUP_F_main_BB__crit_edgeii_203;
LEGUP_F_main_BB__crit_edgeii_203:
		next_state = LEGUP_F_main_BB__crit_edgeii_204;
LEGUP_F_main_BB__crit_edgeii_204:
		next_state = LEGUP_F_main_BB__crit_edgeii_205;
LEGUP_F_main_BB__crit_edgeii_205:
		next_state = LEGUP_F_main_BB__crit_edgeii_206;
LEGUP_F_main_BB__crit_edgeii_206:
		next_state = LEGUP_F_main_BB__crit_edgeii_207;
LEGUP_F_main_BB__crit_edgeii_207:
		next_state = LEGUP_F_main_BB__crit_edgeii_208;
LEGUP_F_main_BB__crit_edgeii_208:
		next_state = LEGUP_F_main_BB__crit_edgeii_209;
LEGUP_F_main_BB__crit_edgeii_209:
		next_state = LEGUP_F_main_BB__crit_edgeii_210;
LEGUP_F_main_BB__crit_edgeii_210:
		next_state = LEGUP_F_main_BB__crit_edgeii_211;
LEGUP_F_main_BB__crit_edgeii_211:
		next_state = LEGUP_F_main_BB__crit_edgeii_212;
LEGUP_F_main_BB__crit_edgeii_212:
		next_state = LEGUP_F_main_BB__crit_edgeii_213;
LEGUP_F_main_BB__crit_edgeii_213:
		next_state = LEGUP_F_main_BB__crit_edgeii_214;
LEGUP_F_main_BB__crit_edgeii_214:
		next_state = LEGUP_F_main_BB__crit_edgeii_215;
LEGUP_F_main_BB__crit_edgeii_215:
		next_state = LEGUP_F_main_BB__crit_edgeii_216;
LEGUP_F_main_BB__crit_edgeii_216:
		next_state = LEGUP_F_main_BB__crit_edgeii_217;
LEGUP_F_main_BB__crit_edgeii_217:
		next_state = LEGUP_F_main_BB__crit_edgeii_218;
LEGUP_F_main_BB__crit_edgeii_218:
		next_state = LEGUP_F_main_BB__crit_edgeii_219;
LEGUP_F_main_BB__crit_edgeii_219:
		next_state = LEGUP_F_main_BB__crit_edgeii_220;
LEGUP_F_main_BB__crit_edgeii_220:
		next_state = LEGUP_F_main_BB__crit_edgeii_221;
LEGUP_F_main_BB__crit_edgeii_221:
		next_state = LEGUP_F_main_BB__crit_edgeii_222;
LEGUP_F_main_BB__crit_edgeii_222:
		next_state = LEGUP_F_main_BB__crit_edgeii_223;
LEGUP_F_main_BB__crit_edgeii_223:
		next_state = LEGUP_F_main_BB__crit_edgeii_224;
LEGUP_F_main_BB__crit_edgeii_224:
		next_state = LEGUP_F_main_BB__crit_edgeii_225;
LEGUP_F_main_BB__crit_edgeii_225:
		next_state = LEGUP_F_main_BB__crit_edgeii_226;
LEGUP_F_main_BB__crit_edgeii_226:
		next_state = LEGUP_F_main_BB__crit_edgeii_227;
LEGUP_F_main_BB__crit_edgeii_227:
		next_state = LEGUP_F_main_BB__crit_edgeii_228;
LEGUP_F_main_BB__crit_edgeii_228:
		next_state = LEGUP_F_main_BB__crit_edgeii_229;
LEGUP_F_main_BB__crit_edgeii_229:
		next_state = LEGUP_F_main_BB__crit_edgeii_230;
LEGUP_F_main_BB__crit_edgeii_230:
	if ((main__crit_edgeii_141 == 1'd1))
		next_state = LEGUP_F_main_BB_lrphi_191;
	else if ((main__crit_edgeii_141 == 1'd0))
		next_state = LEGUP_F_main_BB_insertexitiloopexit_231;
LEGUP_F_main_BB_build_trieexit_234:
		next_state = LEGUP_F_main_BB_build_trieexit_235;
LEGUP_F_main_BB_build_trieexit_235:
		next_state = LEGUP_F_main_BB_build_trieexit_236;
LEGUP_F_main_BB_build_trieexit_236:
		next_state = LEGUP_F_main_BB_build_trieexit_237;
LEGUP_F_main_BB_build_trieexit_237:
		next_state = LEGUP_F_main_BB_build_trieexit_238;
LEGUP_F_main_BB_build_trieexit_238:
		next_state = LEGUP_0;
LEGUP_F_main_BB_build_trieexitloopexit_233:
		next_state = LEGUP_F_main_BB_build_trieexit_234;
LEGUP_F_main_BB_count_frequenciesexitpreheader_12:
		next_state = LEGUP_F_main_BB_count_frequenciesexitpreheader_13;
LEGUP_F_main_BB_count_frequenciesexitpreheader_13:
		next_state = LEGUP_F_main_BB_count_frequenciesexitpreheader_14;
LEGUP_F_main_BB_count_frequenciesexitpreheader_14:
	if ((main_count_frequenciesexitpreheader_14 == 1'd1))
		next_state = LEGUP_F_main_BB__15_15;
	else if ((main_count_frequenciesexitpreheader_14 == 1'd0))
		next_state = LEGUP_F_main_BB_insertexit_99;
LEGUP_F_main_BB_count_frequenciesexitpreheaderpreheader_11:
		next_state = LEGUP_F_main_BB_count_frequenciesexitpreheader_12;
LEGUP_F_main_BB_get_minexit12i_144:
		next_state = LEGUP_F_main_BB_get_minexit12i_145;
LEGUP_F_main_BB_get_minexit12i_145:
		next_state = LEGUP_F_main_BB_get_minexit12i_146;
LEGUP_F_main_BB_get_minexit12i_146:
		next_state = LEGUP_F_main_BB_get_minexit12i_147;
LEGUP_F_main_BB_get_minexit12i_147:
		next_state = LEGUP_F_main_BB_get_minexit12i_148;
LEGUP_F_main_BB_get_minexit12i_148:
	if ((main_get_minexit12i_118_reg == 1'd1))
		next_state = LEGUP_F_main_BB_insertexitithread_149;
	else if ((main_get_minexit12i_118_reg == 1'd0))
		next_state = LEGUP_F_main_BB__120_151;
LEGUP_F_main_BB_get_minexit12iloopexit_143:
		next_state = LEGUP_F_main_BB_get_minexit12i_144;
LEGUP_F_main_BB_get_minexiti_123:
		next_state = LEGUP_F_main_BB_get_minexiti_124;
LEGUP_F_main_BB_get_minexiti_124:
		next_state = LEGUP_F_main_BB_get_minexiti_125;
LEGUP_F_main_BB_get_minexiti_125:
		next_state = LEGUP_F_main_BB_get_minexiti_126;
LEGUP_F_main_BB_get_minexiti_126:
		next_state = LEGUP_F_main_BB_get_minexiti_127;
LEGUP_F_main_BB_get_minexiti_127:
	if ((main_get_minexiti_85_reg == 1'd1))
		next_state = LEGUP_F_main_BB_get_minexit12i_144;
	else if ((main_get_minexiti_85_reg == 1'd0))
		next_state = LEGUP_F_main_BB_lrphii9ipreheader_128;
LEGUP_F_main_BB_get_minexitiloopexit_122:
		next_state = LEGUP_F_main_BB_get_minexiti_123;
LEGUP_F_main_BB_insertexit_99:
	if ((main_insertexit_exitcond2 == 1'd1))
		next_state = LEGUP_F_main_BB__44_100;
	else if ((main_insertexit_exitcond2 == 1'd0))
		next_state = LEGUP_F_main_BB_count_frequenciesexitpreheader_12;
LEGUP_F_main_BB_insertexiti_232:
	if ((main_insertexiti_142 == 1'd1))
		next_state = LEGUP_F_main_BB_lrph14ibackedge_150;
	else if ((main_insertexiti_142 == 1'd0))
		next_state = LEGUP_F_main_BB_build_trieexitloopexit_233;
LEGUP_F_main_BB_insertexitiloopexit_231:
		next_state = LEGUP_F_main_BB_insertexiti_232;
LEGUP_F_main_BB_insertexitithread_149:
		next_state = LEGUP_F_main_BB_lrph14ibackedge_150;
LEGUP_F_main_BB_insertexitloopexit_98:
		next_state = LEGUP_F_main_BB_insertexit_99;
LEGUP_F_main_BB_lrph14i_102:
		next_state = LEGUP_F_main_BB_lrph14i_103;
LEGUP_F_main_BB_lrph14i_103:
		next_state = LEGUP_F_main_BB_lrph14i_104;
LEGUP_F_main_BB_lrph14i_104:
		next_state = LEGUP_F_main_BB_lrph14i_105;
LEGUP_F_main_BB_lrph14i_105:
		next_state = LEGUP_F_main_BB_lrph14i_106;
LEGUP_F_main_BB_lrph14i_106:
	if ((main_lrph14i_54_reg == 1'd1))
		next_state = LEGUP_F_main_BB_get_minexiti_123;
	else if ((main_lrph14i_54_reg == 1'd0))
		next_state = LEGUP_F_main_BB_lrphiiipreheader_107;
LEGUP_F_main_BB_lrph14ibackedge_150:
		next_state = LEGUP_F_main_BB_lrph14i_102;
LEGUP_F_main_BB_lrph14ipreheader_101:
		next_state = LEGUP_F_main_BB_lrph14i_102;
LEGUP_F_main_BB_lrph_58:
		next_state = LEGUP_F_main_BB_lrph_59;
LEGUP_F_main_BB_lrph_59:
		next_state = LEGUP_F_main_BB_lrph_60;
LEGUP_F_main_BB_lrph_60:
	if ((main_lrph_34_reg == 1'd1))
		next_state = LEGUP_F_main_BB__crit_edgei_61;
	else if ((main_lrph_34_reg == 1'd0))
		next_state = LEGUP_F_main_BB_insertexitloopexit_98;
LEGUP_F_main_BB_lrphi_191:
		next_state = LEGUP_F_main_BB_lrphi_192;
LEGUP_F_main_BB_lrphi_192:
		next_state = LEGUP_F_main_BB_lrphi_193;
LEGUP_F_main_BB_lrphi_193:
	if ((main_lrphi_133_reg == 1'd1))
		next_state = LEGUP_F_main_BB__crit_edgeii_194;
	else if ((main_lrphi_133_reg == 1'd0))
		next_state = LEGUP_F_main_BB_insertexitiloopexit_231;
LEGUP_F_main_BB_lrphii9i_129:
	if ((main_lrphii9i_86 == 1'd1))
		next_state = LEGUP_F_main_BB__87_130;
	else if ((main_lrphii9i_86 == 1'd0))
		next_state = LEGUP_F_main_BB__98_135;
LEGUP_F_main_BB_lrphii9ipreheader_128:
		next_state = LEGUP_F_main_BB_lrphii9i_129;
LEGUP_F_main_BB_lrphiii_108:
	if ((main_lrphiii_55 == 1'd1))
		next_state = LEGUP_F_main_BB__56_109;
	else if ((main_lrphiii_55 == 1'd0))
		next_state = LEGUP_F_main_BB__67_114;
LEGUP_F_main_BB_lrphiiipreheader_107:
		next_state = LEGUP_F_main_BB_lrphiii_108;
LEGUP_F_main_BB_lrphipreheader1_190:
		next_state = LEGUP_F_main_BB_lrphi_191;
LEGUP_F_main_BB_lrphipreheader_20:
		next_state = LEGUP_F_main_BB_lrphipreheader_21;
LEGUP_F_main_BB_lrphipreheader_21:
		next_state = LEGUP_F_main_BB_lrphipreheader_22;
LEGUP_F_main_BB_lrphipreheader_22:
		next_state = LEGUP_F_main_BB_lrphipreheader_23;
LEGUP_F_main_BB_lrphipreheader_23:
		next_state = LEGUP_F_main_BB_lrphipreheader_24;
LEGUP_F_main_BB_lrphipreheader_24:
		next_state = LEGUP_F_main_BB_lrphipreheader_25;
LEGUP_F_main_BB_lrphipreheader_25:
		next_state = LEGUP_F_main_BB_lrphipreheader_26;
LEGUP_F_main_BB_lrphipreheader_26:
		next_state = LEGUP_F_main_BB_lrphipreheader_27;
LEGUP_F_main_BB_lrphipreheader_27:
		next_state = LEGUP_F_main_BB_lrphipreheader_28;
LEGUP_F_main_BB_lrphipreheader_28:
		next_state = LEGUP_F_main_BB_lrphipreheader_29;
LEGUP_F_main_BB_lrphipreheader_29:
		next_state = LEGUP_F_main_BB_lrphipreheader_30;
LEGUP_F_main_BB_lrphipreheader_30:
		next_state = LEGUP_F_main_BB_lrphipreheader_31;
LEGUP_F_main_BB_lrphipreheader_31:
		next_state = LEGUP_F_main_BB_lrphipreheader_32;
LEGUP_F_main_BB_lrphipreheader_32:
		next_state = LEGUP_F_main_BB_lrphipreheader_33;
LEGUP_F_main_BB_lrphipreheader_33:
		next_state = LEGUP_F_main_BB_lrphipreheader_34;
LEGUP_F_main_BB_lrphipreheader_34:
		next_state = LEGUP_F_main_BB_lrphipreheader_35;
LEGUP_F_main_BB_lrphipreheader_35:
		next_state = LEGUP_F_main_BB_lrphipreheader_36;
LEGUP_F_main_BB_lrphipreheader_36:
		next_state = LEGUP_F_main_BB_lrphipreheader_37;
LEGUP_F_main_BB_lrphipreheader_37:
		next_state = LEGUP_F_main_BB_lrphipreheader_38;
LEGUP_F_main_BB_lrphipreheader_38:
		next_state = LEGUP_F_main_BB_lrphipreheader_39;
LEGUP_F_main_BB_lrphipreheader_39:
		next_state = LEGUP_F_main_BB_lrphipreheader_40;
LEGUP_F_main_BB_lrphipreheader_40:
		next_state = LEGUP_F_main_BB_lrphipreheader_41;
LEGUP_F_main_BB_lrphipreheader_41:
		next_state = LEGUP_F_main_BB_lrphipreheader_42;
LEGUP_F_main_BB_lrphipreheader_42:
		next_state = LEGUP_F_main_BB_lrphipreheader_43;
LEGUP_F_main_BB_lrphipreheader_43:
		next_state = LEGUP_F_main_BB_lrphipreheader_44;
LEGUP_F_main_BB_lrphipreheader_44:
		next_state = LEGUP_F_main_BB_lrphipreheader_45;
LEGUP_F_main_BB_lrphipreheader_45:
		next_state = LEGUP_F_main_BB_lrphipreheader_46;
LEGUP_F_main_BB_lrphipreheader_46:
		next_state = LEGUP_F_main_BB_lrphipreheader_47;
LEGUP_F_main_BB_lrphipreheader_47:
		next_state = LEGUP_F_main_BB_lrphipreheader_48;
LEGUP_F_main_BB_lrphipreheader_48:
		next_state = LEGUP_F_main_BB_lrphipreheader_49;
LEGUP_F_main_BB_lrphipreheader_49:
		next_state = LEGUP_F_main_BB_lrphipreheader_50;
LEGUP_F_main_BB_lrphipreheader_50:
		next_state = LEGUP_F_main_BB_lrphipreheader_51;
LEGUP_F_main_BB_lrphipreheader_51:
		next_state = LEGUP_F_main_BB_lrphipreheader_52;
LEGUP_F_main_BB_lrphipreheader_52:
		next_state = LEGUP_F_main_BB_lrphipreheader_53;
LEGUP_F_main_BB_lrphipreheader_53:
		next_state = LEGUP_F_main_BB_lrphipreheader_54;
LEGUP_F_main_BB_lrphipreheader_54:
		next_state = LEGUP_F_main_BB_lrphipreheader_55;
LEGUP_F_main_BB_lrphipreheader_55:
		next_state = LEGUP_F_main_BB_lrphipreheader_56;
LEGUP_F_main_BB_lrphipreheader_56:
	if ((main_lrphipreheader_28 == 1'd1))
		next_state = LEGUP_F_main_BB_lrphpreheader_57;
	else if ((main_lrphipreheader_28 == 1'd0))
		next_state = LEGUP_F_main_BB_insertexit_99;
LEGUP_F_main_BB_lrphipreheaderi_153:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_154;
LEGUP_F_main_BB_lrphipreheaderi_154:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_155;
LEGUP_F_main_BB_lrphipreheaderi_155:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_156;
LEGUP_F_main_BB_lrphipreheaderi_156:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_157;
LEGUP_F_main_BB_lrphipreheaderi_157:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_158;
LEGUP_F_main_BB_lrphipreheaderi_158:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_159;
LEGUP_F_main_BB_lrphipreheaderi_159:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_160;
LEGUP_F_main_BB_lrphipreheaderi_160:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_161;
LEGUP_F_main_BB_lrphipreheaderi_161:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_162;
LEGUP_F_main_BB_lrphipreheaderi_162:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_163;
LEGUP_F_main_BB_lrphipreheaderi_163:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_164;
LEGUP_F_main_BB_lrphipreheaderi_164:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_165;
LEGUP_F_main_BB_lrphipreheaderi_165:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_166;
LEGUP_F_main_BB_lrphipreheaderi_166:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_167;
LEGUP_F_main_BB_lrphipreheaderi_167:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_168;
LEGUP_F_main_BB_lrphipreheaderi_168:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_169;
LEGUP_F_main_BB_lrphipreheaderi_169:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_170;
LEGUP_F_main_BB_lrphipreheaderi_170:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_171;
LEGUP_F_main_BB_lrphipreheaderi_171:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_172;
LEGUP_F_main_BB_lrphipreheaderi_172:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_173;
LEGUP_F_main_BB_lrphipreheaderi_173:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_174;
LEGUP_F_main_BB_lrphipreheaderi_174:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_175;
LEGUP_F_main_BB_lrphipreheaderi_175:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_176;
LEGUP_F_main_BB_lrphipreheaderi_176:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_177;
LEGUP_F_main_BB_lrphipreheaderi_177:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_178;
LEGUP_F_main_BB_lrphipreheaderi_178:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_179;
LEGUP_F_main_BB_lrphipreheaderi_179:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_180;
LEGUP_F_main_BB_lrphipreheaderi_180:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_181;
LEGUP_F_main_BB_lrphipreheaderi_181:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_182;
LEGUP_F_main_BB_lrphipreheaderi_182:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_183;
LEGUP_F_main_BB_lrphipreheaderi_183:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_184;
LEGUP_F_main_BB_lrphipreheaderi_184:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_185;
LEGUP_F_main_BB_lrphipreheaderi_185:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_186;
LEGUP_F_main_BB_lrphipreheaderi_186:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_187;
LEGUP_F_main_BB_lrphipreheaderi_187:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_188;
LEGUP_F_main_BB_lrphipreheaderi_188:
		next_state = LEGUP_F_main_BB_lrphipreheaderi_189;
LEGUP_F_main_BB_lrphipreheaderi_189:
	if ((main_lrphipreheaderi_127 == 1'd1))
		next_state = LEGUP_F_main_BB_lrphipreheader1_190;
	else if ((main_lrphipreheaderi_127 == 1'd0))
		next_state = LEGUP_F_main_BB_insertexiti_232;
LEGUP_F_main_BB_lrphpreheader_57:
		next_state = LEGUP_F_main_BB_lrph_58;
default:
	next_state = cur_state;
endcase

end
always @(*) begin
	/* main: %1*/
	/*   %i1.05 = phi i32 [ 0, %0 ], [ %3, %1 ]*/
	if ((((cur_state == LEGUP_0) & (memory_controller_waitrequest == 1'd0)) & (start == 1'd1))) begin
		main_1_i105 = 32'd0;
	end
	/* main: %1*/
	/*   %i1.05 = phi i32 [ 0, %0 ], [ %3, %1 ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__1_3) & (memory_controller_waitrequest == 1'd0)) & (main_1_exitcond5_reg == 1'd0))) */ begin
		main_1_i105 = main_1_3_reg;
	end
end
always @(posedge clk) begin
	/* main: %1*/
	/*   %i1.05 = phi i32 [ 0, %0 ], [ %3, %1 ]*/
	if ((((cur_state == LEGUP_0) & (memory_controller_waitrequest == 1'd0)) & (start == 1'd1))) begin
		main_1_i105_reg <= main_1_i105;
		if (start == 1'b0 && ^(main_1_i105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_i105_reg"); $finish; end
	end
	/* main: %1*/
	/*   %i1.05 = phi i32 [ 0, %0 ], [ %3, %1 ]*/
	if ((((cur_state == LEGUP_F_main_BB__1_3) & (memory_controller_waitrequest == 1'd0)) & (main_1_exitcond5_reg == 1'd0))) begin
		main_1_i105_reg <= main_1_i105;
		if (start == 1'b0 && ^(main_1_i105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_i105_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %1*/
	/*   %2 = trunc i32 %i1.05 to i8*/
		main_1_2 = main_1_i105_reg[7:0];
end
always @(*) begin
	/* main: %1*/
	/*   %scevgep6 = getelementptr [128 x %struct.node]* @alfabeto, i32 0, i32 %i1.05, i32 3*/
		main_1_scevgep6 = (`TAG_g_alfabeto_a + ((16 * main_1_i105_reg) + 12));
end
always @(posedge clk) begin
	/* main: %1*/
	/*   %scevgep6 = getelementptr [128 x %struct.node]* @alfabeto, i32 0, i32 %i1.05, i32 3*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		main_1_scevgep6_reg <= main_1_scevgep6;
		if (start == 1'b0 && ^(main_1_scevgep6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_scevgep6_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %1*/
	/*   %scevgep7 = getelementptr [128 x %struct.node]* @alfabeto, i32 0, i32 %i1.05, i32 2*/
		main_1_scevgep7 = (`TAG_g_alfabeto_a + ((16 * main_1_i105_reg) + 8));
end
always @(posedge clk) begin
	/* main: %1*/
	/*   %scevgep7 = getelementptr [128 x %struct.node]* @alfabeto, i32 0, i32 %i1.05, i32 2*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		main_1_scevgep7_reg <= main_1_scevgep7;
		if (start == 1'b0 && ^(main_1_scevgep7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_scevgep7_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %1*/
	/*   %scevgep89 = getelementptr [128 x %struct.node]* @alfabeto, i32 0, i32 %i1.05, i32 0*/
		main_1_scevgep89 = (`TAG_g_alfabeto_a + (16 * main_1_i105_reg));
end
always @(*) begin
	/* main: %1*/
	/*   %scevgep10 = getelementptr [128 x %struct.node]* @alfabeto, i32 0, i32 %i1.05, i32 1*/
		main_1_scevgep10 = (`TAG_g_alfabeto_a + ((16 * main_1_i105_reg) + 4));
end
always @(*) begin
	/* main: %1*/
	/*   %3 = add nsw i32 %i1.05, 1*/
		main_1_3 = (main_1_i105_reg + 32'd1);
end
always @(posedge clk) begin
	/* main: %1*/
	/*   %3 = add nsw i32 %i1.05, 1*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		main_1_3_reg <= main_1_3;
		if (start == 1'b0 && ^(main_1_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_3_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %1*/
	/*   %exitcond5 = icmp eq i32 %3, 128*/
		main_1_exitcond5 = (main_1_3 == 32'd128);
end
always @(posedge clk) begin
	/* main: %1*/
	/*   %exitcond5 = icmp eq i32 %3, 128*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		main_1_exitcond5_reg <= main_1_exitcond5;
		if (start == 1'b0 && ^(main_1_exitcond5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_exitcond5_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %6*/
	/*   %i1.02.i = phi i32 [ 0, %4 ], [ %12, %6 ]*/
	if (((cur_state == LEGUP_F_main_BB__4_4) & (memory_controller_waitrequest == 1'd0))) begin
		main_6_i102i = 32'd0;
	end
	/* main: %6*/
	/*   %i1.02.i = phi i32 [ 0, %4 ], [ %12, %6 ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__6_10) & (memory_controller_waitrequest == 1'd0)) & (main_6_exitcond_reg == 1'd0))) */ begin
		main_6_i102i = main_6_12_reg;
	end
end
always @(posedge clk) begin
	/* main: %6*/
	/*   %i1.02.i = phi i32 [ 0, %4 ], [ %12, %6 ]*/
	if (((cur_state == LEGUP_F_main_BB__4_4) & (memory_controller_waitrequest == 1'd0))) begin
		main_6_i102i_reg <= main_6_i102i;
		if (start == 1'b0 && ^(main_6_i102i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_6_i102i_reg"); $finish; end
	end
	/* main: %6*/
	/*   %i1.02.i = phi i32 [ 0, %4 ], [ %12, %6 ]*/
	if ((((cur_state == LEGUP_F_main_BB__6_10) & (memory_controller_waitrequest == 1'd0)) & (main_6_exitcond_reg == 1'd0))) begin
		main_6_i102i_reg <= main_6_i102i;
		if (start == 1'b0 && ^(main_6_i102i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_6_i102i_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %6*/
	/*   %scevgep4 = getelementptr [682 x i8]* @texto, i32 0, i32 %i1.02.i*/
		main_6_scevgep4 = (`TAG_g_texto_a + (1 * main_6_i102i_reg));
end
always @(*) begin
	/* main: %6*/
	/*   %7 = load i8* %scevgep4, align 1, !tbaa !10*/
		main_6_7 = memory_controller_out_b[7:0];
end
always @(*) begin
	/* main: %6*/
	/*   %8 = sext i8 %7 to i32*/
		main_6_8 = $signed(main_6_7);
end
always @(*) begin
	/* main: %6*/
	/*   %9 = getelementptr inbounds [128 x %struct.node]* @alfabeto, i32 0, i32 %8, i32 0*/
		main_6_9 = (`TAG_g_alfabeto_a + (16 * main_6_8));
end
always @(posedge clk) begin
	/* main: %6*/
	/*   %9 = getelementptr inbounds [128 x %struct.node]* @alfabeto, i32 0, i32 %8, i32 0*/
	if ((cur_state == LEGUP_F_main_BB__6_7)) begin
		main_6_9_reg <= main_6_9;
		if (start == 1'b0 && ^(main_6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_6_9_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %6*/
	/*   %10 = load i32* %9, align 4, !tbaa !7*/
		main_6_10 = memory_controller_out_a[31:0];
end
always @(*) begin
	/* main: %6*/
	/*   %11 = add nsw i32 %10, 1*/
		main_6_11 = (main_6_10 + 32'd1);
end
always @(*) begin
	/* main: %6*/
	/*   %12 = add nsw i32 %i1.02.i, 1*/
		main_6_12 = (main_6_i102i_reg + 32'd1);
end
always @(posedge clk) begin
	/* main: %6*/
	/*   %12 = add nsw i32 %i1.02.i, 1*/
	if ((cur_state == LEGUP_F_main_BB__6_5)) begin
		main_6_12_reg <= main_6_12;
		if (start == 1'b0 && ^(main_6_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_6_12_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %6*/
	/*   %exitcond = icmp eq i32 %12, 682*/
		main_6_exitcond = (main_6_12 == 32'd682);
end
always @(posedge clk) begin
	/* main: %6*/
	/*   %exitcond = icmp eq i32 %12, 682*/
	if ((cur_state == LEGUP_F_main_BB__6_5)) begin
		main_6_exitcond_reg <= main_6_exitcond;
		if (start == 1'b0 && ^(main_6_exitcond) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_6_exitcond_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %count_frequencies.exit.preheader*/
	/*   %heap_size.0 = phi i32 [ %heap_size.1, %insert.exit ], [ 0, %count_frequencies.exit.preheader.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheaderpreheader_11) & (memory_controller_waitrequest == 1'd0))) begin
		main_count_frequenciesexitpreheader_heap_size0 = 32'd0;
	end
	/* main: %count_frequencies.exit.preheader*/
	/*   %heap_size.0 = phi i32 [ %heap_size.1, %insert.exit ], [ 0, %count_frequencies.exit.preheader.preheader ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB_insertexit_99) & (memory_controller_waitrequest == 1'd0)) & (main_insertexit_exitcond2 == 1'd0))) */ begin
		main_count_frequenciesexitpreheader_heap_size0 = main_insertexit_heap_size1_reg;
	end
end
always @(posedge clk) begin
	/* main: %count_frequencies.exit.preheader*/
	/*   %heap_size.0 = phi i32 [ %heap_size.1, %insert.exit ], [ 0, %count_frequencies.exit.preheader.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheaderpreheader_11) & (memory_controller_waitrequest == 1'd0))) begin
		main_count_frequenciesexitpreheader_heap_size0_reg <= main_count_frequenciesexitpreheader_heap_size0;
		if (start == 1'b0 && ^(main_count_frequenciesexitpreheader_heap_size0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_count_frequenciesexitpreheader_heap_size0_reg"); $finish; end
	end
	/* main: %count_frequencies.exit.preheader*/
	/*   %heap_size.0 = phi i32 [ %heap_size.1, %insert.exit ], [ 0, %count_frequencies.exit.preheader.preheader ]*/
	if ((((cur_state == LEGUP_F_main_BB_insertexit_99) & (memory_controller_waitrequest == 1'd0)) & (main_insertexit_exitcond2 == 1'd0))) begin
		main_count_frequenciesexitpreheader_heap_size0_reg <= main_count_frequenciesexitpreheader_heap_size0;
		if (start == 1'b0 && ^(main_count_frequenciesexitpreheader_heap_size0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_count_frequenciesexitpreheader_heap_size0_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %count_frequencies.exit.preheader*/
	/*   %i2.04 = phi i32 [ %43, %insert.exit ], [ 0, %count_frequencies.exit.preheader.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheaderpreheader_11) & (memory_controller_waitrequest == 1'd0))) begin
		main_count_frequenciesexitpreheader_i204 = 32'd0;
	end
	/* main: %count_frequencies.exit.preheader*/
	/*   %i2.04 = phi i32 [ %43, %insert.exit ], [ 0, %count_frequencies.exit.preheader.preheader ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB_insertexit_99) & (memory_controller_waitrequest == 1'd0)) & (main_insertexit_exitcond2 == 1'd0))) */ begin
		main_count_frequenciesexitpreheader_i204 = main_insertexit_43;
	end
end
always @(posedge clk) begin
	/* main: %count_frequencies.exit.preheader*/
	/*   %i2.04 = phi i32 [ %43, %insert.exit ], [ 0, %count_frequencies.exit.preheader.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheaderpreheader_11) & (memory_controller_waitrequest == 1'd0))) begin
		main_count_frequenciesexitpreheader_i204_reg <= main_count_frequenciesexitpreheader_i204;
		if (start == 1'b0 && ^(main_count_frequenciesexitpreheader_i204) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_count_frequenciesexitpreheader_i204_reg"); $finish; end
	end
	/* main: %count_frequencies.exit.preheader*/
	/*   %i2.04 = phi i32 [ %43, %insert.exit ], [ 0, %count_frequencies.exit.preheader.preheader ]*/
	if ((((cur_state == LEGUP_F_main_BB_insertexit_99) & (memory_controller_waitrequest == 1'd0)) & (main_insertexit_exitcond2 == 1'd0))) begin
		main_count_frequenciesexitpreheader_i204_reg <= main_count_frequenciesexitpreheader_i204;
		if (start == 1'b0 && ^(main_count_frequenciesexitpreheader_i204) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_count_frequenciesexitpreheader_i204_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %count_frequencies.exit.preheader*/
	/*   %scevgep = getelementptr [128 x %struct.node]* @alfabeto, i32 0, i32 %i2.04*/
		main_count_frequenciesexitpreheader_scevgep = (`TAG_g_alfabeto_a + (16 * main_count_frequenciesexitpreheader_i204_reg));
end
always @(posedge clk) begin
	/* main: %count_frequencies.exit.preheader*/
	/*   %scevgep = getelementptr [128 x %struct.node]* @alfabeto, i32 0, i32 %i2.04*/
	if ((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheader_12)) begin
		main_count_frequenciesexitpreheader_scevgep_reg <= main_count_frequenciesexitpreheader_scevgep;
		if (start == 1'b0 && ^(main_count_frequenciesexitpreheader_scevgep) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_count_frequenciesexitpreheader_scevgep_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %count_frequencies.exit.preheader*/
	/*   %scevgep3 = getelementptr inbounds %struct.node* %scevgep, i32 0, i32 0*/
		main_count_frequenciesexitpreheader_scevgep3 = main_count_frequenciesexitpreheader_scevgep;
end
always @(*) begin
	/* main: %count_frequencies.exit.preheader*/
	/*   %13 = load i32* %scevgep3, align 4, !tbaa !7*/
		main_count_frequenciesexitpreheader_13 = memory_controller_out_b[31:0];
end
always @(posedge clk) begin
	/* main: %count_frequencies.exit.preheader*/
	/*   %13 = load i32* %scevgep3, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheader_14)) begin
		main_count_frequenciesexitpreheader_13_reg <= main_count_frequenciesexitpreheader_13;
		if (start == 1'b0 && ^(main_count_frequenciesexitpreheader_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_count_frequenciesexitpreheader_13_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %count_frequencies.exit.preheader*/
	/*   %14 = icmp sgt i32 %13, 0*/
		main_count_frequenciesexitpreheader_14 = ($signed(main_count_frequenciesexitpreheader_13) > $signed(32'd0));
end
always @(*) begin
	/* main: %15*/
	/*   %16 = icmp eq i32 %heap_size.0, 129*/
		main_15_16 = (main_count_frequenciesexitpreheader_heap_size0_reg == 32'd129);
end
always @(*) begin
	/* main: %19*/
	/*   %20 = add nsw i32 %heap_size.0, 1*/
		main_19_20 = (main_count_frequenciesexitpreheader_heap_size0_reg + 32'd1);
end
always @(posedge clk) begin
	/* main: %19*/
	/*   %20 = add nsw i32 %heap_size.0, 1*/
	if ((cur_state == LEGUP_F_main_BB__19_17)) begin
		main_19_20_reg <= main_19_20;
		if (start == 1'b0 && ^(main_19_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_19_20_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %19*/
	/*   %21 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %20*/
		main_19_21 = (`TAG_g_heap_a + (4 * main_19_20_reg));
end
always @(*) begin
	/* main: %19*/
	/*   %22 = icmp sgt i32 %heap_size.0, 0*/
		main_19_22 = ($signed(main_count_frequenciesexitpreheader_heap_size0_reg) > $signed(32'd0));
end
always @(posedge clk) begin
	/* main: %19*/
	/*   %22 = icmp sgt i32 %heap_size.0, 0*/
	if ((cur_state == LEGUP_F_main_BB__19_17)) begin
		main_19_22_reg <= main_19_22;
		if (start == 1'b0 && ^(main_19_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_19_22_reg"); $finish; end
	end
end
always @(*) begin
	main_lrphipreheader_23 = main_signed_divide_32_0;
end
always @(posedge clk) begin
	/* main: %.lr.ph.i.preheader*/
	/*   %23 = sdiv i32 %20, 2*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_52)) begin
		main_lrphipreheader_23_reg <= main_lrphipreheader_23;
		if (start == 1'b0 && ^(main_lrphipreheader_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphipreheader_23_reg"); $finish; end
	end
	/* main: %.lr.ph.i.preheader*/
	/*   %23 = sdiv i32 %20, 2*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_52)) begin
		main_lrphipreheader_23_reg <= main_lrphipreheader_23;
		if (start == 1'b0 && ^(main_lrphipreheader_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphipreheader_23_reg"); $finish; end
	end
	/* main: %.lr.ph.i.preheader.i*/
	/*   %122 = sdiv i32 %53, 2*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_185)) begin
		main_lrphipreheader_23_reg <= main_lrphipreheaderi_122;
		if (start == 1'b0 && ^(main_lrphipreheaderi_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphipreheader_23_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i.preheader*/
	/*   %24 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %23*/
		main_lrphipreheader_24 = (`TAG_g_heap_a + (4 * main_lrphipreheader_23));
end
always @(posedge clk) begin
	/* main: %.lr.ph.i.preheader*/
	/*   %24 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %23*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_52)) begin
		main_lrphipreheader_24_reg <= main_lrphipreheader_24;
		if (start == 1'b0 && ^(main_lrphipreheader_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphipreheader_24_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i.preheader*/
	/*   %25 = load %struct.node** %24, align 4, !tbaa !11*/
		main_lrphipreheader_25 = memory_controller_out_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %.lr.ph.i.preheader*/
	/*   %25 = load %struct.node** %24, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_54)) begin
		main_lrphipreheader_25_reg <= main_lrphipreheader_25;
		if (start == 1'b0 && ^(main_lrphipreheader_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphipreheader_25_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i.preheader*/
	/*   %26 = getelementptr inbounds %struct.node* %25, i32 0, i32 0*/
		main_lrphipreheader_26 = main_lrphipreheader_25;
end
always @(*) begin
	/* main: %.lr.ph.i.preheader*/
	/*   %27 = load i32* %26, align 4, !tbaa !7*/
		main_lrphipreheader_27 = memory_controller_out_a[31:0];
end
always @(*) begin
	/* main: %.lr.ph.i.preheader*/
	/*   %28 = icmp sgt i32 %27, %13*/
		main_lrphipreheader_28 = ($signed(main_lrphipreheader_27) > $signed(main_count_frequenciesexitpreheader_13_reg));
end
always @(*) begin
	/* main: %.lr.ph*/
	/*   %29 = phi %struct.node* [ %37, %._crit_edge.i ], [ %25, %.lr.ph.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphpreheader_57) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph_29 = main_lrphipreheader_25_reg;
	end
	/* main: %.lr.ph*/
	/*   %29 = phi %struct.node* [ %37, %._crit_edge.i ], [ %25, %.lr.ph.preheader ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__crit_edgei_97) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgei_42 == 1'd1))) */ begin
		main_lrph_29 = main__crit_edgei_37_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph*/
	/*   %29 = phi %struct.node* [ %37, %._crit_edge.i ], [ %25, %.lr.ph.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphpreheader_57) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph_29_reg <= main_lrph_29;
		if (start == 1'b0 && ^(main_lrph_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_29_reg"); $finish; end
	end
	/* main: %.lr.ph*/
	/*   %29 = phi %struct.node* [ %37, %._crit_edge.i ], [ %25, %.lr.ph.preheader ]*/
	if ((((cur_state == LEGUP_F_main_BB__crit_edgei_97) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgei_42 == 1'd1))) begin
		main_lrph_29_reg <= main_lrph_29;
		if (start == 1'b0 && ^(main_lrph_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_29_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph*/
	/*   %30 = phi %struct.node** [ %36, %._crit_edge.i ], [ %24, %.lr.ph.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphpreheader_57) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph_30 = main_lrphipreheader_24_reg;
	end
	/* main: %.lr.ph*/
	/*   %30 = phi %struct.node** [ %36, %._crit_edge.i ], [ %24, %.lr.ph.preheader ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__crit_edgei_97) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgei_42 == 1'd1))) */ begin
		main_lrph_30 = main__crit_edgei_36_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph*/
	/*   %30 = phi %struct.node** [ %36, %._crit_edge.i ], [ %24, %.lr.ph.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphpreheader_57) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph_30_reg <= main_lrph_30;
		if (start == 1'b0 && ^(main_lrph_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_30_reg"); $finish; end
	end
	/* main: %.lr.ph*/
	/*   %30 = phi %struct.node** [ %36, %._crit_edge.i ], [ %24, %.lr.ph.preheader ]*/
	if ((((cur_state == LEGUP_F_main_BB__crit_edgei_97) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgei_42 == 1'd1))) begin
		main_lrph_30_reg <= main_lrph_30;
		if (start == 1'b0 && ^(main_lrph_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_30_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph*/
	/*   %31 = phi i32 [ %35, %._crit_edge.i ], [ %23, %.lr.ph.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphpreheader_57) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph_31 = main_lrphipreheader_23_reg;
	end
	/* main: %.lr.ph*/
	/*   %31 = phi i32 [ %35, %._crit_edge.i ], [ %23, %.lr.ph.preheader ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__crit_edgei_97) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgei_42 == 1'd1))) */ begin
		main_lrph_31 = main__crit_edgei_35_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph*/
	/*   %31 = phi i32 [ %35, %._crit_edge.i ], [ %23, %.lr.ph.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphpreheader_57) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph_31_reg <= main_lrph_31;
		if (start == 1'b0 && ^(main_lrph_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_31_reg"); $finish; end
	end
	/* main: %.lr.ph*/
	/*   %31 = phi i32 [ %35, %._crit_edge.i ], [ %23, %.lr.ph.preheader ]*/
	if ((((cur_state == LEGUP_F_main_BB__crit_edgei_97) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgei_42 == 1'd1))) begin
		main_lrph_31_reg <= main_lrph_31;
		if (start == 1'b0 && ^(main_lrph_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_31_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph*/
	/*   %p.01.i3 = phi i32 [ %31, %._crit_edge.i ], [ %20, %.lr.ph.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphpreheader_57) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph_p01i3 = main_19_20_reg;
	end
	/* main: %.lr.ph*/
	/*   %p.01.i3 = phi i32 [ %31, %._crit_edge.i ], [ %20, %.lr.ph.preheader ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__crit_edgei_97) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgei_42 == 1'd1))) */ begin
		main_lrph_p01i3 = main_lrph_31_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph*/
	/*   %p.01.i3 = phi i32 [ %31, %._crit_edge.i ], [ %20, %.lr.ph.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphpreheader_57) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph_p01i3_reg <= main_lrph_p01i3;
		if (start == 1'b0 && ^(main_lrph_p01i3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_p01i3_reg"); $finish; end
	end
	/* main: %.lr.ph*/
	/*   %p.01.i3 = phi i32 [ %31, %._crit_edge.i ], [ %20, %.lr.ph.preheader ]*/
	if ((((cur_state == LEGUP_F_main_BB__crit_edgei_97) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgei_42 == 1'd1))) begin
		main_lrph_p01i3_reg <= main_lrph_p01i3;
		if (start == 1'b0 && ^(main_lrph_p01i3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_p01i3_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph*/
	/*   %32 = phi %struct.node* [ %.pre.i, %._crit_edge.i ], [ %scevgep, %.lr.ph.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphpreheader_57) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph_32 = main_count_frequenciesexitpreheader_scevgep_reg;
	end
	/* main: %.lr.ph*/
	/*   %32 = phi %struct.node* [ %.pre.i, %._crit_edge.i ], [ %scevgep, %.lr.ph.preheader ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__crit_edgei_97) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgei_42 == 1'd1))) */ begin
		main_lrph_32 = main__crit_edgei_prei_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph*/
	/*   %32 = phi %struct.node* [ %.pre.i, %._crit_edge.i ], [ %scevgep, %.lr.ph.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphpreheader_57) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph_32_reg <= main_lrph_32;
		if (start == 1'b0 && ^(main_lrph_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_32_reg"); $finish; end
	end
	/* main: %.lr.ph*/
	/*   %32 = phi %struct.node* [ %.pre.i, %._crit_edge.i ], [ %scevgep, %.lr.ph.preheader ]*/
	if ((((cur_state == LEGUP_F_main_BB__crit_edgei_97) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgei_42 == 1'd1))) begin
		main_lrph_32_reg <= main_lrph_32;
		if (start == 1'b0 && ^(main_lrph_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_32_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph*/
	/*   %33 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %p.01.i3*/
		main_lrph_33 = (`TAG_g_heap_a + (4 * main_lrph_p01i3_reg));
end
always @(posedge clk) begin
	/* main: %.lr.ph*/
	/*   %33 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %p.01.i3*/
	if ((cur_state == LEGUP_F_main_BB_lrph_58)) begin
		main_lrph_33_reg <= main_lrph_33;
		if (start == 1'b0 && ^(main_lrph_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_33_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph*/
	/*   %34 = icmp sgt i32 %p.01.i3, 3*/
		main_lrph_34 = ($signed(main_lrph_p01i3_reg) > $signed(32'd3));
end
always @(posedge clk) begin
	/* main: %.lr.ph*/
	/*   %34 = icmp sgt i32 %p.01.i3, 3*/
	if ((cur_state == LEGUP_F_main_BB_lrph_58)) begin
		main_lrph_34_reg <= main_lrph_34;
		if (start == 1'b0 && ^(main_lrph_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph_34_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %._crit_edge.i*/
	/*   %.pre.i = load %struct.node** %30, align 4, !tbaa !11*/
		main__crit_edgei_prei = memory_controller_out_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %._crit_edge.i*/
	/*   %.pre.i = load %struct.node** %30, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_63)) begin
		main__crit_edgei_prei_reg <= main__crit_edgei_prei;
		if (start == 1'b0 && ^(main__crit_edgei_prei) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgei_prei_reg"); $finish; end
	end
end
always @(*) begin
	main__crit_edgei_35 = main_signed_divide_32_0;
end
always @(posedge clk) begin
	/* main: %._crit_edge.i*/
	/*   %35 = sdiv i32 %31, 2*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_93)) begin
		main__crit_edgei_35_reg <= main__crit_edgei_35;
		if (start == 1'b0 && ^(main__crit_edgei_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgei_35_reg"); $finish; end
	end
	/* main: %._crit_edge.i*/
	/*   %35 = sdiv i32 %31, 2*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_93)) begin
		main__crit_edgei_35_reg <= main__crit_edgei_35;
		if (start == 1'b0 && ^(main__crit_edgei_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgei_35_reg"); $finish; end
	end
	/* main: %._crit_edge.i.i*/
	/*   %134 = sdiv i32 %130, 2*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_226)) begin
		main__crit_edgei_35_reg <= main__crit_edgeii_134;
		if (start == 1'b0 && ^(main__crit_edgeii_134) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgei_35_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %._crit_edge.i*/
	/*   %36 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %35*/
		main__crit_edgei_36 = (`TAG_g_heap_a + (4 * main__crit_edgei_35));
end
always @(posedge clk) begin
	/* main: %._crit_edge.i*/
	/*   %36 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %35*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_93)) begin
		main__crit_edgei_36_reg <= main__crit_edgei_36;
		if (start == 1'b0 && ^(main__crit_edgei_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgei_36_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %._crit_edge.i*/
	/*   %37 = load %struct.node** %36, align 4, !tbaa !11*/
		main__crit_edgei_37 = memory_controller_out_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %._crit_edge.i*/
	/*   %37 = load %struct.node** %36, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_95)) begin
		main__crit_edgei_37_reg <= main__crit_edgei_37;
		if (start == 1'b0 && ^(main__crit_edgei_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgei_37_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %._crit_edge.i*/
	/*   %38 = getelementptr inbounds %struct.node* %37, i32 0, i32 0*/
		main__crit_edgei_38 = main__crit_edgei_37;
end
always @(*) begin
	/* main: %._crit_edge.i*/
	/*   %39 = load i32* %38, align 4, !tbaa !7*/
		main__crit_edgei_39 = memory_controller_out_b[31:0];
end
always @(*) begin
	/* main: %._crit_edge.i*/
	/*   %40 = getelementptr inbounds %struct.node* %.pre.i, i32 0, i32 0*/
		main__crit_edgei_40 = main__crit_edgei_prei;
end
always @(posedge clk) begin
	/* main: %._crit_edge.i*/
	/*   %40 = getelementptr inbounds %struct.node* %.pre.i, i32 0, i32 0*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_63)) begin
		main__crit_edgei_40_reg <= main__crit_edgei_40;
		if (start == 1'b0 && ^(main__crit_edgei_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgei_40_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %._crit_edge.i*/
	/*   %41 = load i32* %40, align 4, !tbaa !7*/
		main__crit_edgei_41 = memory_controller_out_a[31:0];
end
always @(posedge clk) begin
	/* main: %._crit_edge.i*/
	/*   %41 = load i32* %40, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_96)) begin
		main__crit_edgei_41_reg <= main__crit_edgei_41;
		if (start == 1'b0 && ^(main__crit_edgei_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgei_41_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %._crit_edge.i*/
	/*   %42 = icmp sgt i32 %39, %41*/
		main__crit_edgei_42 = ($signed(main__crit_edgei_39) > $signed(main__crit_edgei_41_reg));
end
always @(*) begin
	/* main: %insert.exit*/
	/*   %heap_size.1 = phi i32 [ 129, %17 ], [ %20, %.lr.ph.i.preheader ], [ %20, %19 ], [ %heap_size.0, %count_frequencies.exit.preheader ], [ %20, %insert.exit.loopexit ]*/
	if ((((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheader_14) & (memory_controller_waitrequest == 1'd0)) & (main_count_frequenciesexitpreheader_14 == 1'd0))) begin
		main_insertexit_heap_size1 = main_count_frequenciesexitpreheader_heap_size0_reg;
	end
	/* main: %insert.exit*/
	/*   %heap_size.1 = phi i32 [ 129, %17 ], [ %20, %.lr.ph.i.preheader ], [ %20, %19 ], [ %heap_size.0, %count_frequencies.exit.preheader ], [ %20, %insert.exit.loopexit ]*/
	else if (((cur_state == LEGUP_F_main_BB__17_16) & (memory_controller_waitrequest == 1'd0))) begin
		main_insertexit_heap_size1 = 32'd129;
	end
	/* main: %insert.exit*/
	/*   %heap_size.1 = phi i32 [ 129, %17 ], [ %20, %.lr.ph.i.preheader ], [ %20, %19 ], [ %heap_size.0, %count_frequencies.exit.preheader ], [ %20, %insert.exit.loopexit ]*/
	else if ((((cur_state == LEGUP_F_main_BB__19_19) & (memory_controller_waitrequest == 1'd0)) & (main_19_22_reg == 1'd0))) begin
		main_insertexit_heap_size1 = main_19_20_reg;
	end
	/* main: %insert.exit*/
	/*   %heap_size.1 = phi i32 [ 129, %17 ], [ %20, %.lr.ph.i.preheader ], [ %20, %19 ], [ %heap_size.0, %count_frequencies.exit.preheader ], [ %20, %insert.exit.loopexit ]*/
	else if ((((cur_state == LEGUP_F_main_BB_lrphipreheader_56) & (memory_controller_waitrequest == 1'd0)) & (main_lrphipreheader_28 == 1'd0))) begin
		main_insertexit_heap_size1 = main_19_20_reg;
	end
	/* main: %insert.exit*/
	/*   %heap_size.1 = phi i32 [ 129, %17 ], [ %20, %.lr.ph.i.preheader ], [ %20, %19 ], [ %heap_size.0, %count_frequencies.exit.preheader ], [ %20, %insert.exit.loopexit ]*/
	else /* if (((cur_state == LEGUP_F_main_BB_insertexitloopexit_98) & (memory_controller_waitrequest == 1'd0))) */ begin
		main_insertexit_heap_size1 = main_19_20_reg;
	end
end
always @(posedge clk) begin
	/* main: %insert.exit*/
	/*   %heap_size.1 = phi i32 [ 129, %17 ], [ %20, %.lr.ph.i.preheader ], [ %20, %19 ], [ %heap_size.0, %count_frequencies.exit.preheader ], [ %20, %insert.exit.loopexit ]*/
	if ((((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheader_14) & (memory_controller_waitrequest == 1'd0)) & (main_count_frequenciesexitpreheader_14 == 1'd0))) begin
		main_insertexit_heap_size1_reg <= main_insertexit_heap_size1;
		if (start == 1'b0 && ^(main_insertexit_heap_size1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_insertexit_heap_size1_reg"); $finish; end
	end
	/* main: %insert.exit*/
	/*   %heap_size.1 = phi i32 [ 129, %17 ], [ %20, %.lr.ph.i.preheader ], [ %20, %19 ], [ %heap_size.0, %count_frequencies.exit.preheader ], [ %20, %insert.exit.loopexit ]*/
	if (((cur_state == LEGUP_F_main_BB__17_16) & (memory_controller_waitrequest == 1'd0))) begin
		main_insertexit_heap_size1_reg <= main_insertexit_heap_size1;
		if (start == 1'b0 && ^(main_insertexit_heap_size1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_insertexit_heap_size1_reg"); $finish; end
	end
	/* main: %insert.exit*/
	/*   %heap_size.1 = phi i32 [ 129, %17 ], [ %20, %.lr.ph.i.preheader ], [ %20, %19 ], [ %heap_size.0, %count_frequencies.exit.preheader ], [ %20, %insert.exit.loopexit ]*/
	if ((((cur_state == LEGUP_F_main_BB__19_19) & (memory_controller_waitrequest == 1'd0)) & (main_19_22_reg == 1'd0))) begin
		main_insertexit_heap_size1_reg <= main_insertexit_heap_size1;
		if (start == 1'b0 && ^(main_insertexit_heap_size1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_insertexit_heap_size1_reg"); $finish; end
	end
	/* main: %insert.exit*/
	/*   %heap_size.1 = phi i32 [ 129, %17 ], [ %20, %.lr.ph.i.preheader ], [ %20, %19 ], [ %heap_size.0, %count_frequencies.exit.preheader ], [ %20, %insert.exit.loopexit ]*/
	if ((((cur_state == LEGUP_F_main_BB_lrphipreheader_56) & (memory_controller_waitrequest == 1'd0)) & (main_lrphipreheader_28 == 1'd0))) begin
		main_insertexit_heap_size1_reg <= main_insertexit_heap_size1;
		if (start == 1'b0 && ^(main_insertexit_heap_size1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_insertexit_heap_size1_reg"); $finish; end
	end
	/* main: %insert.exit*/
	/*   %heap_size.1 = phi i32 [ 129, %17 ], [ %20, %.lr.ph.i.preheader ], [ %20, %19 ], [ %heap_size.0, %count_frequencies.exit.preheader ], [ %20, %insert.exit.loopexit ]*/
	if (((cur_state == LEGUP_F_main_BB_insertexitloopexit_98) & (memory_controller_waitrequest == 1'd0))) begin
		main_insertexit_heap_size1_reg <= main_insertexit_heap_size1;
		if (start == 1'b0 && ^(main_insertexit_heap_size1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_insertexit_heap_size1_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %insert.exit*/
	/*   %43 = add nsw i32 %i2.04, 1*/
		main_insertexit_43 = (main_count_frequenciesexitpreheader_i204_reg + 32'd1);
end
always @(*) begin
	/* main: %insert.exit*/
	/*   %exitcond2 = icmp eq i32 %43, 128*/
		main_insertexit_exitcond2 = (main_insertexit_43 == 32'd128);
end
always @(*) begin
	/* main: %44*/
	/*   %47 = icmp sgt i32 %heap_size.1, 1*/
		main_44_47 = ($signed(main_insertexit_heap_size1_reg) > $signed(32'd1));
end
always @(*) begin
	/* main: %.lr.ph14.i*/
	/*   %used_intermediaries.0 = phi i32 [ 0, %.lr.ph14.i.preheader ], [ %used_intermediaries.0.be, %.lr.ph14.i.backedge ]*/
	if (((cur_state == LEGUP_F_main_BB_lrph14ipreheader_101) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph14i_used_intermediaries0 = 32'd0;
	end
	/* main: %.lr.ph14.i*/
	/*   %used_intermediaries.0 = phi i32 [ 0, %.lr.ph14.i.preheader ], [ %used_intermediaries.0.be, %.lr.ph14.i.backedge ]*/
	else /* if (((cur_state == LEGUP_F_main_BB_lrph14ibackedge_150) & (memory_controller_waitrequest == 1'd0))) */ begin
		main_lrph14i_used_intermediaries0 = main_lrph14ibackedge_used_intermediaries0be;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph14.i*/
	/*   %used_intermediaries.0 = phi i32 [ 0, %.lr.ph14.i.preheader ], [ %used_intermediaries.0.be, %.lr.ph14.i.backedge ]*/
	if (((cur_state == LEGUP_F_main_BB_lrph14ipreheader_101) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph14i_used_intermediaries0_reg <= main_lrph14i_used_intermediaries0;
		if (start == 1'b0 && ^(main_lrph14i_used_intermediaries0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph14i_used_intermediaries0_reg"); $finish; end
	end
	/* main: %.lr.ph14.i*/
	/*   %used_intermediaries.0 = phi i32 [ 0, %.lr.ph14.i.preheader ], [ %used_intermediaries.0.be, %.lr.ph14.i.backedge ]*/
	if (((cur_state == LEGUP_F_main_BB_lrph14ibackedge_150) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph14i_used_intermediaries0_reg <= main_lrph14i_used_intermediaries0;
		if (start == 1'b0 && ^(main_lrph14i_used_intermediaries0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph14i_used_intermediaries0_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph14.i*/
	/*   %48 = phi i32 [ %heap_size.1, %.lr.ph14.i.preheader ], [ %.be, %.lr.ph14.i.backedge ]*/
	if (((cur_state == LEGUP_F_main_BB_lrph14ipreheader_101) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph14i_48 = main_insertexit_heap_size1_reg;
	end
	/* main: %.lr.ph14.i*/
	/*   %48 = phi i32 [ %heap_size.1, %.lr.ph14.i.preheader ], [ %.be, %.lr.ph14.i.backedge ]*/
	else /* if (((cur_state == LEGUP_F_main_BB_lrph14ibackedge_150) & (memory_controller_waitrequest == 1'd0))) */ begin
		main_lrph14i_48 = main_lrph14ibackedge_be_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph14.i*/
	/*   %48 = phi i32 [ %heap_size.1, %.lr.ph14.i.preheader ], [ %.be, %.lr.ph14.i.backedge ]*/
	if (((cur_state == LEGUP_F_main_BB_lrph14ipreheader_101) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph14i_48_reg <= main_lrph14i_48;
		if (start == 1'b0 && ^(main_lrph14i_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph14i_48_reg"); $finish; end
	end
	/* main: %.lr.ph14.i*/
	/*   %48 = phi i32 [ %heap_size.1, %.lr.ph14.i.preheader ], [ %.be, %.lr.ph14.i.backedge ]*/
	if (((cur_state == LEGUP_F_main_BB_lrph14ibackedge_150) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph14i_48_reg <= main_lrph14i_48;
		if (start == 1'b0 && ^(main_lrph14i_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph14i_48_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph14.i*/
	/*   %49 = getelementptr inbounds [128 x %struct.node]* @intermediarios, i32 0, i32 %used_intermediaries.0*/
		main_lrph14i_49 = (`TAG_g_intermediarios_a + (16 * main_lrph14i_used_intermediaries0_reg));
end
always @(posedge clk) begin
	/* main: %.lr.ph14.i*/
	/*   %49 = getelementptr inbounds [128 x %struct.node]* @intermediarios, i32 0, i32 %used_intermediaries.0*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		main_lrph14i_49_reg <= main_lrph14i_49;
		if (start == 1'b0 && ^(main_lrph14i_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph14i_49_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph14.i*/
	/*   %50 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
		main_lrph14i_50 = memory_controller_out_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %.lr.ph14.i*/
	/*   %50 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_104)) begin
		main_lrph14i_50_reg <= main_lrph14i_50;
		if (start == 1'b0 && ^(main_lrph14i_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph14i_50_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph14.i*/
	/*   %51 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %48*/
		main_lrph14i_51 = (`TAG_g_heap_a + (4 * main_lrph14i_48_reg));
end
always @(posedge clk) begin
	/* main: %.lr.ph14.i*/
	/*   %51 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %48*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		main_lrph14i_51_reg <= main_lrph14i_51;
		if (start == 1'b0 && ^(main_lrph14i_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph14i_51_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph14.i*/
	/*   %52 = load %struct.node** %51, align 4, !tbaa !11*/
		main_lrph14i_52 = memory_controller_out_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(*) begin
	/* main: %.lr.ph14.i*/
	/*   %53 = add nsw i32 %48, -1*/
		main_lrph14i_53 = (main_lrph14i_48_reg + -32'd1);
end
always @(posedge clk) begin
	/* main: %.lr.ph14.i*/
	/*   %53 = add nsw i32 %48, -1*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		main_lrph14i_53_reg <= main_lrph14i_53;
		if (start == 1'b0 && ^(main_lrph14i_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph14i_53_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph14.i*/
	/*   %54 = icmp slt i32 %48, 3*/
		main_lrph14i_54 = ($signed(main_lrph14i_48_reg) < $signed(32'd3));
end
always @(posedge clk) begin
	/* main: %.lr.ph14.i*/
	/*   %54 = icmp slt i32 %48, 3*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		main_lrph14i_54_reg <= main_lrph14i_54;
		if (start == 1'b0 && ^(main_lrph14i_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph14i_54_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i.i.i*/
	/*   %filho.02.i.i.i = phi i32 [ %78, %77 ], [ 2, %.lr.ph.i.i.i.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphiiipreheader_107) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphiii_filho02iii = 32'd2;
	end
	/* main: %.lr.ph.i.i.i*/
	/*   %filho.02.i.i.i = phi i32 [ %78, %77 ], [ 2, %.lr.ph.i.i.i.preheader ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__77_121) & (memory_controller_waitrequest == 1'd0)) & (main_77_79_reg == 1'd0))) */ begin
		main_lrphiii_filho02iii = main_77_78_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph.i.i.i*/
	/*   %filho.02.i.i.i = phi i32 [ %78, %77 ], [ 2, %.lr.ph.i.i.i.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphiiipreheader_107) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphiii_filho02iii_reg <= main_lrphiii_filho02iii;
		if (start == 1'b0 && ^(main_lrphiii_filho02iii) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphiii_filho02iii_reg"); $finish; end
	end
	/* main: %.lr.ph.i.i.i*/
	/*   %filho.02.i.i.i = phi i32 [ %78, %77 ], [ 2, %.lr.ph.i.i.i.preheader ]*/
	if ((((cur_state == LEGUP_F_main_BB__77_121) & (memory_controller_waitrequest == 1'd0)) & (main_77_79_reg == 1'd0))) begin
		main_lrphiii_filho02iii_reg <= main_lrphiii_filho02iii;
		if (start == 1'b0 && ^(main_lrphiii_filho02iii) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphiii_filho02iii_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i.i.i*/
	/*   %pai.01.i.i.i = phi i32 [ %filho.1.i.i.i, %77 ], [ 1, %.lr.ph.i.i.i.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphiiipreheader_107) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphiii_pai01iii = 32'd1;
	end
	/* main: %.lr.ph.i.i.i*/
	/*   %pai.01.i.i.i = phi i32 [ %filho.1.i.i.i, %77 ], [ 1, %.lr.ph.i.i.i.preheader ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__77_121) & (memory_controller_waitrequest == 1'd0)) & (main_77_79_reg == 1'd0))) */ begin
		main_lrphiii_pai01iii = main_67_filho1iii_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph.i.i.i*/
	/*   %pai.01.i.i.i = phi i32 [ %filho.1.i.i.i, %77 ], [ 1, %.lr.ph.i.i.i.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphiiipreheader_107) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphiii_pai01iii_reg <= main_lrphiii_pai01iii;
		if (start == 1'b0 && ^(main_lrphiii_pai01iii) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphiii_pai01iii_reg"); $finish; end
	end
	/* main: %.lr.ph.i.i.i*/
	/*   %pai.01.i.i.i = phi i32 [ %filho.1.i.i.i, %77 ], [ 1, %.lr.ph.i.i.i.preheader ]*/
	if ((((cur_state == LEGUP_F_main_BB__77_121) & (memory_controller_waitrequest == 1'd0)) & (main_77_79_reg == 1'd0))) begin
		main_lrphiii_pai01iii_reg <= main_lrphiii_pai01iii;
		if (start == 1'b0 && ^(main_lrphiii_pai01iii) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphiii_pai01iii_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i.i.i*/
	/*   %55 = icmp slt i32 %filho.02.i.i.i, %53*/
		main_lrphiii_55 = ($signed(main_lrphiii_filho02iii_reg) < $signed(main_lrph14i_53_reg));
end
always @(*) begin
	/* main: %56*/
	/*   %57 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %filho.02.i.i.i*/
		main_56_57 = (`TAG_g_heap_a + (4 * main_lrphiii_filho02iii_reg));
end
always @(*) begin
	/* main: %56*/
	/*   %58 = load %struct.node** %57, align 4, !tbaa !11*/
		main_56_58 = memory_controller_out_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(*) begin
	/* main: %56*/
	/*   %59 = getelementptr inbounds %struct.node* %58, i32 0, i32 0*/
		main_56_59 = main_56_58;
end
always @(*) begin
	/* main: %56*/
	/*   %60 = load i32* %59, align 4, !tbaa !7*/
		main_56_60 = memory_controller_out_a[31:0];
end
always @(*) begin
	/* main: %56*/
	/*   %61 = or i32 %filho.02.i.i.i, 1*/
		main_56_61 = (main_lrphiii_filho02iii_reg | 32'd1);
end
always @(posedge clk) begin
	/* main: %56*/
	/*   %61 = or i32 %filho.02.i.i.i, 1*/
	if ((cur_state == LEGUP_F_main_BB__56_109)) begin
		main_56_61_reg <= main_56_61;
		if (start == 1'b0 && ^(main_56_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_56_61_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %56*/
	/*   %62 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %61*/
		main_56_62 = (`TAG_g_heap_a + (4 * main_56_61));
end
always @(*) begin
	/* main: %56*/
	/*   %63 = load %struct.node** %62, align 4, !tbaa !11*/
		main_56_63 = memory_controller_out_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(*) begin
	/* main: %56*/
	/*   %64 = getelementptr inbounds %struct.node* %63, i32 0, i32 0*/
		main_56_64 = main_56_63;
end
always @(*) begin
	/* main: %56*/
	/*   %65 = load i32* %64, align 4, !tbaa !7*/
		main_56_65 = memory_controller_out_b[31:0];
end
always @(*) begin
	/* main: %56*/
	/*   %66 = icmp sgt i32 %60, %65*/
		main_56_66 = ($signed(main_56_60) > $signed(main_56_65));
end
always @(*) begin
	/* main: %56*/
	/*   %.filho.0.i.i.i = select i1 %66, i32 %61, i32 %filho.02.i.i.i*/
		main_56_filho0iii = (main_56_66 ? main_56_61_reg : main_lrphiii_filho02iii_reg);
end
always @(*) begin
	/* main: %67*/
	/*   %filho.1.i.i.i = phi i32 [ %filho.02.i.i.i, %.lr.ph.i.i.i ], [ %.filho.0.i.i.i, %56 ]*/
	if ((((cur_state == LEGUP_F_main_BB_lrphiii_108) & (memory_controller_waitrequest == 1'd0)) & (main_lrphiii_55 == 1'd0))) begin
		main_67_filho1iii = main_lrphiii_filho02iii_reg;
	end
	/* main: %67*/
	/*   %filho.1.i.i.i = phi i32 [ %filho.02.i.i.i, %.lr.ph.i.i.i ], [ %.filho.0.i.i.i, %56 ]*/
	else /* if (((cur_state == LEGUP_F_main_BB__56_113) & (memory_controller_waitrequest == 1'd0))) */ begin
		main_67_filho1iii = main_56_filho0iii;
	end
end
always @(posedge clk) begin
	/* main: %67*/
	/*   %filho.1.i.i.i = phi i32 [ %filho.02.i.i.i, %.lr.ph.i.i.i ], [ %.filho.0.i.i.i, %56 ]*/
	if ((((cur_state == LEGUP_F_main_BB_lrphiii_108) & (memory_controller_waitrequest == 1'd0)) & (main_lrphiii_55 == 1'd0))) begin
		main_67_filho1iii_reg <= main_67_filho1iii;
		if (start == 1'b0 && ^(main_67_filho1iii) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_67_filho1iii_reg"); $finish; end
	end
	/* main: %67*/
	/*   %filho.1.i.i.i = phi i32 [ %filho.02.i.i.i, %.lr.ph.i.i.i ], [ %.filho.0.i.i.i, %56 ]*/
	if (((cur_state == LEGUP_F_main_BB__56_113) & (memory_controller_waitrequest == 1'd0))) begin
		main_67_filho1iii_reg <= main_67_filho1iii;
		if (start == 1'b0 && ^(main_67_filho1iii) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_67_filho1iii_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %67*/
	/*   %68 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %filho.1.i.i.i*/
		main_67_68 = (`TAG_g_heap_a + (4 * main_67_filho1iii_reg));
end
always @(posedge clk) begin
	/* main: %67*/
	/*   %68 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %filho.1.i.i.i*/
	if ((cur_state == LEGUP_F_main_BB__67_114)) begin
		main_67_68_reg <= main_67_68;
		if (start == 1'b0 && ^(main_67_68) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_67_68_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %67*/
	/*   %69 = load %struct.node** %68, align 4, !tbaa !11*/
		main_67_69 = memory_controller_out_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %67*/
	/*   %69 = load %struct.node** %68, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__67_116)) begin
		main_67_69_reg <= main_67_69;
		if (start == 1'b0 && ^(main_67_69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_67_69_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %67*/
	/*   %70 = getelementptr inbounds %struct.node* %69, i32 0, i32 0*/
		main_67_70 = main_67_69;
end
always @(*) begin
	/* main: %67*/
	/*   %71 = load i32* %70, align 4, !tbaa !7*/
		main_67_71 = memory_controller_out_a[31:0];
end
always @(*) begin
	/* main: %67*/
	/*   %72 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %pai.01.i.i.i*/
		main_67_72 = (`TAG_g_heap_a + (4 * main_lrphiii_pai01iii_reg));
end
always @(posedge clk) begin
	/* main: %67*/
	/*   %72 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %pai.01.i.i.i*/
	if ((cur_state == LEGUP_F_main_BB__67_114)) begin
		main_67_72_reg <= main_67_72;
		if (start == 1'b0 && ^(main_67_72) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_67_72_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %67*/
	/*   %73 = load %struct.node** %72, align 4, !tbaa !11*/
		main_67_73 = memory_controller_out_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %67*/
	/*   %73 = load %struct.node** %72, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__67_116)) begin
		main_67_73_reg <= main_67_73;
		if (start == 1'b0 && ^(main_67_73) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_67_73_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %67*/
	/*   %74 = getelementptr inbounds %struct.node* %73, i32 0, i32 0*/
		main_67_74 = main_67_73;
end
always @(*) begin
	/* main: %67*/
	/*   %75 = load i32* %74, align 4, !tbaa !7*/
		main_67_75 = memory_controller_out_b[31:0];
end
always @(*) begin
	/* main: %67*/
	/*   %76 = icmp slt i32 %71, %75*/
		main_67_76 = ($signed(main_67_71) < $signed(main_67_75));
end
always @(*) begin
	/* main: %77*/
	/*   %78 = shl nsw i32 %filho.1.i.i.i, 1*/
		main_77_78 = (main_67_filho1iii_reg <<< (32'd1 % 32));
end
always @(posedge clk) begin
	/* main: %77*/
	/*   %78 = shl nsw i32 %filho.1.i.i.i, 1*/
	if ((cur_state == LEGUP_F_main_BB__77_119)) begin
		main_77_78_reg <= main_77_78;
		if (start == 1'b0 && ^(main_77_78) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_77_78_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %77*/
	/*   %79 = icmp sgt i32 %78, %53*/
		main_77_79 = ($signed(main_77_78) > $signed(main_lrph14i_53_reg));
end
always @(posedge clk) begin
	/* main: %77*/
	/*   %79 = icmp sgt i32 %78, %53*/
	if ((cur_state == LEGUP_F_main_BB__77_119)) begin
		main_77_79_reg <= main_77_79;
		if (start == 1'b0 && ^(main_77_79) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_77_79_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %get_min.exit.i*/
	/*   %80 = getelementptr inbounds [128 x %struct.node]* @intermediarios, i32 0, i32 %used_intermediaries.0, i32 2*/
		main_get_minexiti_80 = (`TAG_g_intermediarios_a + ((16 * main_lrph14i_used_intermediaries0_reg) + 8));
end
always @(posedge clk) begin
	/* main: %get_min.exit.i*/
	/*   %80 = getelementptr inbounds [128 x %struct.node]* @intermediarios, i32 0, i32 %used_intermediaries.0, i32 2*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		main_get_minexiti_80_reg <= main_get_minexiti_80;
		if (start == 1'b0 && ^(main_get_minexiti_80) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_get_minexiti_80_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %get_min.exit.i*/
	/*   %81 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
		main_get_minexiti_81 = memory_controller_out_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %get_min.exit.i*/
	/*   %81 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_125)) begin
		main_get_minexiti_81_reg <= main_get_minexiti_81;
		if (start == 1'b0 && ^(main_get_minexiti_81) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_get_minexiti_81_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %get_min.exit.i*/
	/*   %82 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %53*/
		main_get_minexiti_82 = (`TAG_g_heap_a + (4 * main_lrph14i_53_reg));
end
always @(posedge clk) begin
	/* main: %get_min.exit.i*/
	/*   %82 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %53*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		main_get_minexiti_82_reg <= main_get_minexiti_82;
		if (start == 1'b0 && ^(main_get_minexiti_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_get_minexiti_82_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %get_min.exit.i*/
	/*   %83 = load %struct.node** %82, align 4, !tbaa !11*/
		main_get_minexiti_83 = memory_controller_out_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(*) begin
	/* main: %get_min.exit.i*/
	/*   %84 = add nsw i32 %48, -2*/
		main_get_minexiti_84 = (main_lrph14i_48_reg + -32'd2);
end
always @(posedge clk) begin
	/* main: %get_min.exit.i*/
	/*   %84 = add nsw i32 %48, -2*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		main_get_minexiti_84_reg <= main_get_minexiti_84;
		if (start == 1'b0 && ^(main_get_minexiti_84) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_get_minexiti_84_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %get_min.exit.i*/
	/*   %85 = icmp slt i32 %48, 4*/
		main_get_minexiti_85 = ($signed(main_lrph14i_48_reg) < $signed(32'd4));
end
always @(posedge clk) begin
	/* main: %get_min.exit.i*/
	/*   %85 = icmp slt i32 %48, 4*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		main_get_minexiti_85_reg <= main_get_minexiti_85;
		if (start == 1'b0 && ^(main_get_minexiti_85) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_get_minexiti_85_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i.i9.i*/
	/*   %filho.02.i.i7.i = phi i32 [ %109, %108 ], [ 2, %.lr.ph.i.i9.i.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphii9ipreheader_128) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphii9i_filho02ii7i = 32'd2;
	end
	/* main: %.lr.ph.i.i9.i*/
	/*   %filho.02.i.i7.i = phi i32 [ %109, %108 ], [ 2, %.lr.ph.i.i9.i.preheader ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__108_142) & (memory_controller_waitrequest == 1'd0)) & (main_108_110_reg == 1'd0))) */ begin
		main_lrphii9i_filho02ii7i = main_108_109_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph.i.i9.i*/
	/*   %filho.02.i.i7.i = phi i32 [ %109, %108 ], [ 2, %.lr.ph.i.i9.i.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphii9ipreheader_128) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphii9i_filho02ii7i_reg <= main_lrphii9i_filho02ii7i;
		if (start == 1'b0 && ^(main_lrphii9i_filho02ii7i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphii9i_filho02ii7i_reg"); $finish; end
	end
	/* main: %.lr.ph.i.i9.i*/
	/*   %filho.02.i.i7.i = phi i32 [ %109, %108 ], [ 2, %.lr.ph.i.i9.i.preheader ]*/
	if ((((cur_state == LEGUP_F_main_BB__108_142) & (memory_controller_waitrequest == 1'd0)) & (main_108_110_reg == 1'd0))) begin
		main_lrphii9i_filho02ii7i_reg <= main_lrphii9i_filho02ii7i;
		if (start == 1'b0 && ^(main_lrphii9i_filho02ii7i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphii9i_filho02ii7i_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i.i9.i*/
	/*   %pai.01.i.i8.i = phi i32 [ %filho.1.i.i11.i, %108 ], [ 1, %.lr.ph.i.i9.i.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphii9ipreheader_128) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphii9i_pai01ii8i = 32'd1;
	end
	/* main: %.lr.ph.i.i9.i*/
	/*   %pai.01.i.i8.i = phi i32 [ %filho.1.i.i11.i, %108 ], [ 1, %.lr.ph.i.i9.i.preheader ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__108_142) & (memory_controller_waitrequest == 1'd0)) & (main_108_110_reg == 1'd0))) */ begin
		main_lrphii9i_pai01ii8i = main_98_filho1ii11i_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph.i.i9.i*/
	/*   %pai.01.i.i8.i = phi i32 [ %filho.1.i.i11.i, %108 ], [ 1, %.lr.ph.i.i9.i.preheader ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphii9ipreheader_128) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphii9i_pai01ii8i_reg <= main_lrphii9i_pai01ii8i;
		if (start == 1'b0 && ^(main_lrphii9i_pai01ii8i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphii9i_pai01ii8i_reg"); $finish; end
	end
	/* main: %.lr.ph.i.i9.i*/
	/*   %pai.01.i.i8.i = phi i32 [ %filho.1.i.i11.i, %108 ], [ 1, %.lr.ph.i.i9.i.preheader ]*/
	if ((((cur_state == LEGUP_F_main_BB__108_142) & (memory_controller_waitrequest == 1'd0)) & (main_108_110_reg == 1'd0))) begin
		main_lrphii9i_pai01ii8i_reg <= main_lrphii9i_pai01ii8i;
		if (start == 1'b0 && ^(main_lrphii9i_pai01ii8i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphii9i_pai01ii8i_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i.i9.i*/
	/*   %86 = icmp slt i32 %filho.02.i.i7.i, %84*/
		main_lrphii9i_86 = ($signed(main_lrphii9i_filho02ii7i_reg) < $signed(main_get_minexiti_84_reg));
end
always @(*) begin
	/* main: %87*/
	/*   %88 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %filho.02.i.i7.i*/
		main_87_88 = (`TAG_g_heap_a + (4 * main_lrphii9i_filho02ii7i_reg));
end
always @(*) begin
	/* main: %87*/
	/*   %89 = load %struct.node** %88, align 4, !tbaa !11*/
		main_87_89 = memory_controller_out_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(*) begin
	/* main: %87*/
	/*   %90 = getelementptr inbounds %struct.node* %89, i32 0, i32 0*/
		main_87_90 = main_87_89;
end
always @(*) begin
	/* main: %87*/
	/*   %91 = load i32* %90, align 4, !tbaa !7*/
		main_87_91 = memory_controller_out_a[31:0];
end
always @(*) begin
	/* main: %87*/
	/*   %92 = or i32 %filho.02.i.i7.i, 1*/
		main_87_92 = (main_lrphii9i_filho02ii7i_reg | 32'd1);
end
always @(posedge clk) begin
	/* main: %87*/
	/*   %92 = or i32 %filho.02.i.i7.i, 1*/
	if ((cur_state == LEGUP_F_main_BB__87_130)) begin
		main_87_92_reg <= main_87_92;
		if (start == 1'b0 && ^(main_87_92) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_87_92_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %87*/
	/*   %93 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %92*/
		main_87_93 = (`TAG_g_heap_a + (4 * main_87_92));
end
always @(*) begin
	/* main: %87*/
	/*   %94 = load %struct.node** %93, align 4, !tbaa !11*/
		main_87_94 = memory_controller_out_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(*) begin
	/* main: %87*/
	/*   %95 = getelementptr inbounds %struct.node* %94, i32 0, i32 0*/
		main_87_95 = main_87_94;
end
always @(*) begin
	/* main: %87*/
	/*   %96 = load i32* %95, align 4, !tbaa !7*/
		main_87_96 = memory_controller_out_b[31:0];
end
always @(*) begin
	/* main: %87*/
	/*   %97 = icmp sgt i32 %91, %96*/
		main_87_97 = ($signed(main_87_91) > $signed(main_87_96));
end
always @(*) begin
	/* main: %87*/
	/*   %.filho.0.i.i10.i = select i1 %97, i32 %92, i32 %filho.02.i.i7.i*/
		main_87_filho0ii10i = (main_87_97 ? main_87_92_reg : main_lrphii9i_filho02ii7i_reg);
end
always @(*) begin
	/* main: %98*/
	/*   %filho.1.i.i11.i = phi i32 [ %filho.02.i.i7.i, %.lr.ph.i.i9.i ], [ %.filho.0.i.i10.i, %87 ]*/
	if ((((cur_state == LEGUP_F_main_BB_lrphii9i_129) & (memory_controller_waitrequest == 1'd0)) & (main_lrphii9i_86 == 1'd0))) begin
		main_98_filho1ii11i = main_lrphii9i_filho02ii7i_reg;
	end
	/* main: %98*/
	/*   %filho.1.i.i11.i = phi i32 [ %filho.02.i.i7.i, %.lr.ph.i.i9.i ], [ %.filho.0.i.i10.i, %87 ]*/
	else /* if (((cur_state == LEGUP_F_main_BB__87_134) & (memory_controller_waitrequest == 1'd0))) */ begin
		main_98_filho1ii11i = main_87_filho0ii10i;
	end
end
always @(posedge clk) begin
	/* main: %98*/
	/*   %filho.1.i.i11.i = phi i32 [ %filho.02.i.i7.i, %.lr.ph.i.i9.i ], [ %.filho.0.i.i10.i, %87 ]*/
	if ((((cur_state == LEGUP_F_main_BB_lrphii9i_129) & (memory_controller_waitrequest == 1'd0)) & (main_lrphii9i_86 == 1'd0))) begin
		main_98_filho1ii11i_reg <= main_98_filho1ii11i;
		if (start == 1'b0 && ^(main_98_filho1ii11i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_98_filho1ii11i_reg"); $finish; end
	end
	/* main: %98*/
	/*   %filho.1.i.i11.i = phi i32 [ %filho.02.i.i7.i, %.lr.ph.i.i9.i ], [ %.filho.0.i.i10.i, %87 ]*/
	if (((cur_state == LEGUP_F_main_BB__87_134) & (memory_controller_waitrequest == 1'd0))) begin
		main_98_filho1ii11i_reg <= main_98_filho1ii11i;
		if (start == 1'b0 && ^(main_98_filho1ii11i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_98_filho1ii11i_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %98*/
	/*   %99 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %filho.1.i.i11.i*/
		main_98_99 = (`TAG_g_heap_a + (4 * main_98_filho1ii11i_reg));
end
always @(posedge clk) begin
	/* main: %98*/
	/*   %99 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %filho.1.i.i11.i*/
	if ((cur_state == LEGUP_F_main_BB__98_135)) begin
		main_98_99_reg <= main_98_99;
		if (start == 1'b0 && ^(main_98_99) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_98_99_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %98*/
	/*   %100 = load %struct.node** %99, align 4, !tbaa !11*/
		main_98_100 = memory_controller_out_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %98*/
	/*   %100 = load %struct.node** %99, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__98_137)) begin
		main_98_100_reg <= main_98_100;
		if (start == 1'b0 && ^(main_98_100) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_98_100_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %98*/
	/*   %101 = getelementptr inbounds %struct.node* %100, i32 0, i32 0*/
		main_98_101 = main_98_100;
end
always @(*) begin
	/* main: %98*/
	/*   %102 = load i32* %101, align 4, !tbaa !7*/
		main_98_102 = memory_controller_out_a[31:0];
end
always @(*) begin
	/* main: %98*/
	/*   %103 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %pai.01.i.i8.i*/
		main_98_103 = (`TAG_g_heap_a + (4 * main_lrphii9i_pai01ii8i_reg));
end
always @(posedge clk) begin
	/* main: %98*/
	/*   %103 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %pai.01.i.i8.i*/
	if ((cur_state == LEGUP_F_main_BB__98_135)) begin
		main_98_103_reg <= main_98_103;
		if (start == 1'b0 && ^(main_98_103) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_98_103_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %98*/
	/*   %104 = load %struct.node** %103, align 4, !tbaa !11*/
		main_98_104 = memory_controller_out_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %98*/
	/*   %104 = load %struct.node** %103, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__98_137)) begin
		main_98_104_reg <= main_98_104;
		if (start == 1'b0 && ^(main_98_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_98_104_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %98*/
	/*   %105 = getelementptr inbounds %struct.node* %104, i32 0, i32 0*/
		main_98_105 = main_98_104;
end
always @(*) begin
	/* main: %98*/
	/*   %106 = load i32* %105, align 4, !tbaa !7*/
		main_98_106 = memory_controller_out_b[31:0];
end
always @(*) begin
	/* main: %98*/
	/*   %107 = icmp slt i32 %102, %106*/
		main_98_107 = ($signed(main_98_102) < $signed(main_98_106));
end
always @(*) begin
	/* main: %108*/
	/*   %109 = shl nsw i32 %filho.1.i.i11.i, 1*/
		main_108_109 = (main_98_filho1ii11i_reg <<< (32'd1 % 32));
end
always @(posedge clk) begin
	/* main: %108*/
	/*   %109 = shl nsw i32 %filho.1.i.i11.i, 1*/
	if ((cur_state == LEGUP_F_main_BB__108_140)) begin
		main_108_109_reg <= main_108_109;
		if (start == 1'b0 && ^(main_108_109) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_108_109_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %108*/
	/*   %110 = icmp sgt i32 %109, %84*/
		main_108_110 = ($signed(main_108_109) > $signed(main_get_minexiti_84_reg));
end
always @(posedge clk) begin
	/* main: %108*/
	/*   %110 = icmp sgt i32 %109, %84*/
	if ((cur_state == LEGUP_F_main_BB__108_140)) begin
		main_108_110_reg <= main_108_110;
		if (start == 1'b0 && ^(main_108_110) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_108_110_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %get_min.exit12.i*/
	/*   %111 = getelementptr inbounds [128 x %struct.node]* @intermediarios, i32 0, i32 %used_intermediaries.0, i32 3*/
		main_get_minexit12i_111 = (`TAG_g_intermediarios_a + ((16 * main_lrph14i_used_intermediaries0_reg) + 12));
end
always @(*) begin
	/* main: %get_min.exit12.i*/
	/*   %112 = getelementptr inbounds %struct.node* %50, i32 0, i32 0*/
		main_get_minexit12i_112 = main_lrph14i_50_reg;
end
always @(posedge clk) begin
	/* main: %get_min.exit12.i*/
	/*   %112 = getelementptr inbounds %struct.node* %50, i32 0, i32 0*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_144)) begin
		main_get_minexit12i_112_reg <= main_get_minexit12i_112;
		if (start == 1'b0 && ^(main_get_minexit12i_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_get_minexit12i_112_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %get_min.exit12.i*/
	/*   %113 = load i32* %112, align 4, !tbaa !7*/
		main_get_minexit12i_113 = memory_controller_out_a[31:0];
end
always @(*) begin
	/* main: %get_min.exit12.i*/
	/*   %114 = getelementptr inbounds %struct.node* %81, i32 0, i32 0*/
		main_get_minexit12i_114 = main_get_minexiti_81_reg;
end
always @(posedge clk) begin
	/* main: %get_min.exit12.i*/
	/*   %114 = getelementptr inbounds %struct.node* %81, i32 0, i32 0*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_144)) begin
		main_get_minexit12i_114_reg <= main_get_minexit12i_114;
		if (start == 1'b0 && ^(main_get_minexit12i_114) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_get_minexit12i_114_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %get_min.exit12.i*/
	/*   %115 = load i32* %114, align 4, !tbaa !7*/
		main_get_minexit12i_115 = memory_controller_out_b[31:0];
end
always @(*) begin
	/* main: %get_min.exit12.i*/
	/*   %116 = add nsw i32 %115, %113*/
		main_get_minexit12i_116 = (main_get_minexit12i_115 + main_get_minexit12i_113);
end
always @(posedge clk) begin
	/* main: %get_min.exit12.i*/
	/*   %116 = add nsw i32 %115, %113*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_147)) begin
		main_get_minexit12i_116_reg <= main_get_minexit12i_116;
		if (start == 1'b0 && ^(main_get_minexit12i_116) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_get_minexit12i_116_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %get_min.exit12.i*/
	/*   %117 = getelementptr inbounds %struct.node* %49, i32 0, i32 0*/
		main_get_minexit12i_117 = main_lrph14i_49_reg;
end
always @(posedge clk) begin
	/* main: %get_min.exit12.i*/
	/*   %117 = getelementptr inbounds %struct.node* %49, i32 0, i32 0*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_144)) begin
		main_get_minexit12i_117_reg <= main_get_minexit12i_117;
		if (start == 1'b0 && ^(main_get_minexit12i_117) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_get_minexit12i_117_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %get_min.exit12.i*/
	/*   %118 = icmp eq i32 %84, 129*/
		main_get_minexit12i_118 = (main_get_minexiti_84_reg == 32'd129);
end
always @(posedge clk) begin
	/* main: %get_min.exit12.i*/
	/*   %118 = icmp eq i32 %84, 129*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_144)) begin
		main_get_minexit12i_118_reg <= main_get_minexit12i_118;
		if (start == 1'b0 && ^(main_get_minexit12i_118) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_get_minexit12i_118_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph14.i.backedge*/
	/*   %.be = phi i32 [ %53, %insert.exit.i ], [ 129, %insert.exit.i.thread ]*/
	if (((cur_state == LEGUP_F_main_BB_insertexitithread_149) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph14ibackedge_be = 32'd129;
	end
	/* main: %.lr.ph14.i.backedge*/
	/*   %.be = phi i32 [ %53, %insert.exit.i ], [ 129, %insert.exit.i.thread ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB_insertexiti_232) & (memory_controller_waitrequest == 1'd0)) & (main_insertexiti_142 == 1'd1))) */ begin
		main_lrph14ibackedge_be = main_lrph14i_53_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph14.i.backedge*/
	/*   %.be = phi i32 [ %53, %insert.exit.i ], [ 129, %insert.exit.i.thread ]*/
	if (((cur_state == LEGUP_F_main_BB_insertexitithread_149) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrph14ibackedge_be_reg <= main_lrph14ibackedge_be;
		if (start == 1'b0 && ^(main_lrph14ibackedge_be) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph14ibackedge_be_reg"); $finish; end
	end
	/* main: %.lr.ph14.i.backedge*/
	/*   %.be = phi i32 [ %53, %insert.exit.i ], [ 129, %insert.exit.i.thread ]*/
	if ((((cur_state == LEGUP_F_main_BB_insertexiti_232) & (memory_controller_waitrequest == 1'd0)) & (main_insertexiti_142 == 1'd1))) begin
		main_lrph14ibackedge_be_reg <= main_lrph14ibackedge_be;
		if (start == 1'b0 && ^(main_lrph14ibackedge_be) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrph14ibackedge_be_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph14.i.backedge*/
	/*   %used_intermediaries.0.be = add nsw i32 %used_intermediaries.0, 1*/
		main_lrph14ibackedge_used_intermediaries0be = (main_lrph14i_used_intermediaries0_reg + 32'd1);
end
always @(*) begin
	/* main: %120*/
	/*   %121 = icmp sgt i32 %84, 0*/
		main_120_121 = ($signed(main_get_minexiti_84_reg) > $signed(32'd0));
end
always @(posedge clk) begin
	/* main: %120*/
	/*   %121 = icmp sgt i32 %84, 0*/
	if ((cur_state == LEGUP_F_main_BB__120_151)) begin
		main_120_121_reg <= main_120_121;
		if (start == 1'b0 && ^(main_120_121) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_120_121_reg"); $finish; end
	end
end
always @(*) begin
	main_lrphipreheaderi_122 = main_signed_divide_32_0;
end
always @(*) begin
/* main: %.lr.ph.i.preheader.i*/
/*   %122 = sdiv i32 %53, 2*/
	main_lrphipreheaderi_122_reg = main_lrphipreheader_23_reg;
end
always @(*) begin
	/* main: %.lr.ph.i.preheader.i*/
	/*   %123 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %122*/
		main_lrphipreheaderi_123 = (`TAG_g_heap_a + (4 * main_lrphipreheaderi_122));
end
always @(posedge clk) begin
	/* main: %.lr.ph.i.preheader.i*/
	/*   %123 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %122*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_185)) begin
		main_lrphipreheaderi_123_reg <= main_lrphipreheaderi_123;
		if (start == 1'b0 && ^(main_lrphipreheaderi_123) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphipreheaderi_123_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i.preheader.i*/
	/*   %124 = load %struct.node** %123, align 4, !tbaa !11*/
		main_lrphipreheaderi_124 = memory_controller_out_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %.lr.ph.i.preheader.i*/
	/*   %124 = load %struct.node** %123, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_187)) begin
		main_lrphipreheaderi_124_reg <= main_lrphipreheaderi_124;
		if (start == 1'b0 && ^(main_lrphipreheaderi_124) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphipreheaderi_124_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i.preheader.i*/
	/*   %125 = getelementptr inbounds %struct.node* %124, i32 0, i32 0*/
		main_lrphipreheaderi_125 = main_lrphipreheaderi_124;
end
always @(*) begin
	/* main: %.lr.ph.i.preheader.i*/
	/*   %126 = load i32* %125, align 4, !tbaa !7*/
		main_lrphipreheaderi_126 = memory_controller_out_a[31:0];
end
always @(*) begin
	/* main: %.lr.ph.i.preheader.i*/
	/*   %127 = icmp sgt i32 %126, %116*/
		main_lrphipreheaderi_127 = ($signed(main_lrphipreheaderi_126) > $signed(main_get_minexit12i_116_reg));
end
always @(*) begin
	/* main: %.lr.ph.i*/
	/*   %128 = phi %struct.node* [ %136, %._crit_edge.i.i ], [ %124, %.lr.ph.i.preheader1 ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphipreheader1_190) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphi_128 = main_lrphipreheaderi_124_reg;
	end
	/* main: %.lr.ph.i*/
	/*   %128 = phi %struct.node* [ %136, %._crit_edge.i.i ], [ %124, %.lr.ph.i.preheader1 ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__crit_edgeii_230) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgeii_141 == 1'd1))) */ begin
		main_lrphi_128 = main__crit_edgeii_136_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph.i*/
	/*   %128 = phi %struct.node* [ %136, %._crit_edge.i.i ], [ %124, %.lr.ph.i.preheader1 ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphipreheader1_190) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphi_128_reg <= main_lrphi_128;
		if (start == 1'b0 && ^(main_lrphi_128) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_128_reg"); $finish; end
	end
	/* main: %.lr.ph.i*/
	/*   %128 = phi %struct.node* [ %136, %._crit_edge.i.i ], [ %124, %.lr.ph.i.preheader1 ]*/
	if ((((cur_state == LEGUP_F_main_BB__crit_edgeii_230) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgeii_141 == 1'd1))) begin
		main_lrphi_128_reg <= main_lrphi_128;
		if (start == 1'b0 && ^(main_lrphi_128) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_128_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i*/
	/*   %129 = phi %struct.node** [ %135, %._crit_edge.i.i ], [ %123, %.lr.ph.i.preheader1 ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphipreheader1_190) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphi_129 = main_lrphipreheaderi_123_reg;
	end
	/* main: %.lr.ph.i*/
	/*   %129 = phi %struct.node** [ %135, %._crit_edge.i.i ], [ %123, %.lr.ph.i.preheader1 ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__crit_edgeii_230) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgeii_141 == 1'd1))) */ begin
		main_lrphi_129 = main__crit_edgeii_135_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph.i*/
	/*   %129 = phi %struct.node** [ %135, %._crit_edge.i.i ], [ %123, %.lr.ph.i.preheader1 ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphipreheader1_190) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphi_129_reg <= main_lrphi_129;
		if (start == 1'b0 && ^(main_lrphi_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_129_reg"); $finish; end
	end
	/* main: %.lr.ph.i*/
	/*   %129 = phi %struct.node** [ %135, %._crit_edge.i.i ], [ %123, %.lr.ph.i.preheader1 ]*/
	if ((((cur_state == LEGUP_F_main_BB__crit_edgeii_230) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgeii_141 == 1'd1))) begin
		main_lrphi_129_reg <= main_lrphi_129;
		if (start == 1'b0 && ^(main_lrphi_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_129_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i*/
	/*   %130 = phi i32 [ %134, %._crit_edge.i.i ], [ %122, %.lr.ph.i.preheader1 ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphipreheader1_190) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphi_130 = main_lrphipreheaderi_122_reg;
	end
	/* main: %.lr.ph.i*/
	/*   %130 = phi i32 [ %134, %._crit_edge.i.i ], [ %122, %.lr.ph.i.preheader1 ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__crit_edgeii_230) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgeii_141 == 1'd1))) */ begin
		main_lrphi_130 = main__crit_edgeii_134_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph.i*/
	/*   %130 = phi i32 [ %134, %._crit_edge.i.i ], [ %122, %.lr.ph.i.preheader1 ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphipreheader1_190) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphi_130_reg <= main_lrphi_130;
		if (start == 1'b0 && ^(main_lrphi_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_130_reg"); $finish; end
	end
	/* main: %.lr.ph.i*/
	/*   %130 = phi i32 [ %134, %._crit_edge.i.i ], [ %122, %.lr.ph.i.preheader1 ]*/
	if ((((cur_state == LEGUP_F_main_BB__crit_edgeii_230) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgeii_141 == 1'd1))) begin
		main_lrphi_130_reg <= main_lrphi_130;
		if (start == 1'b0 && ^(main_lrphi_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_130_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i*/
	/*   %p.01.i13.i = phi i32 [ %130, %._crit_edge.i.i ], [ %53, %.lr.ph.i.preheader1 ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphipreheader1_190) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphi_p01i13i = main_lrph14i_53_reg;
	end
	/* main: %.lr.ph.i*/
	/*   %p.01.i13.i = phi i32 [ %130, %._crit_edge.i.i ], [ %53, %.lr.ph.i.preheader1 ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__crit_edgeii_230) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgeii_141 == 1'd1))) */ begin
		main_lrphi_p01i13i = main_lrphi_130_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph.i*/
	/*   %p.01.i13.i = phi i32 [ %130, %._crit_edge.i.i ], [ %53, %.lr.ph.i.preheader1 ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphipreheader1_190) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphi_p01i13i_reg <= main_lrphi_p01i13i;
		if (start == 1'b0 && ^(main_lrphi_p01i13i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_p01i13i_reg"); $finish; end
	end
	/* main: %.lr.ph.i*/
	/*   %p.01.i13.i = phi i32 [ %130, %._crit_edge.i.i ], [ %53, %.lr.ph.i.preheader1 ]*/
	if ((((cur_state == LEGUP_F_main_BB__crit_edgeii_230) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgeii_141 == 1'd1))) begin
		main_lrphi_p01i13i_reg <= main_lrphi_p01i13i;
		if (start == 1'b0 && ^(main_lrphi_p01i13i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_p01i13i_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i*/
	/*   %131 = phi %struct.node* [ %.pre.i.i, %._crit_edge.i.i ], [ %49, %.lr.ph.i.preheader1 ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphipreheader1_190) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphi_131 = main_lrph14i_49_reg;
	end
	/* main: %.lr.ph.i*/
	/*   %131 = phi %struct.node* [ %.pre.i.i, %._crit_edge.i.i ], [ %49, %.lr.ph.i.preheader1 ]*/
	else /* if ((((cur_state == LEGUP_F_main_BB__crit_edgeii_230) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgeii_141 == 1'd1))) */ begin
		main_lrphi_131 = main__crit_edgeii_preii_reg;
	end
end
always @(posedge clk) begin
	/* main: %.lr.ph.i*/
	/*   %131 = phi %struct.node* [ %.pre.i.i, %._crit_edge.i.i ], [ %49, %.lr.ph.i.preheader1 ]*/
	if (((cur_state == LEGUP_F_main_BB_lrphipreheader1_190) & (memory_controller_waitrequest == 1'd0))) begin
		main_lrphi_131_reg <= main_lrphi_131;
		if (start == 1'b0 && ^(main_lrphi_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_131_reg"); $finish; end
	end
	/* main: %.lr.ph.i*/
	/*   %131 = phi %struct.node* [ %.pre.i.i, %._crit_edge.i.i ], [ %49, %.lr.ph.i.preheader1 ]*/
	if ((((cur_state == LEGUP_F_main_BB__crit_edgeii_230) & (memory_controller_waitrequest == 1'd0)) & (main__crit_edgeii_141 == 1'd1))) begin
		main_lrphi_131_reg <= main_lrphi_131;
		if (start == 1'b0 && ^(main_lrphi_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_131_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i*/
	/*   %132 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %p.01.i13.i*/
		main_lrphi_132 = (`TAG_g_heap_a + (4 * main_lrphi_p01i13i_reg));
end
always @(posedge clk) begin
	/* main: %.lr.ph.i*/
	/*   %132 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %p.01.i13.i*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_191)) begin
		main_lrphi_132_reg <= main_lrphi_132;
		if (start == 1'b0 && ^(main_lrphi_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_132_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %.lr.ph.i*/
	/*   %133 = icmp sgt i32 %p.01.i13.i, 3*/
		main_lrphi_133 = ($signed(main_lrphi_p01i13i_reg) > $signed(32'd3));
end
always @(posedge clk) begin
	/* main: %.lr.ph.i*/
	/*   %133 = icmp sgt i32 %p.01.i13.i, 3*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_191)) begin
		main_lrphi_133_reg <= main_lrphi_133;
		if (start == 1'b0 && ^(main_lrphi_133) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_lrphi_133_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %._crit_edge.i.i*/
	/*   %.pre.i.i = load %struct.node** %129, align 4, !tbaa !11*/
		main__crit_edgeii_preii = memory_controller_out_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %._crit_edge.i.i*/
	/*   %.pre.i.i = load %struct.node** %129, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_196)) begin
		main__crit_edgeii_preii_reg <= main__crit_edgeii_preii;
		if (start == 1'b0 && ^(main__crit_edgeii_preii) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgeii_preii_reg"); $finish; end
	end
end
always @(*) begin
	main__crit_edgeii_134 = main_signed_divide_32_0;
end
always @(*) begin
/* main: %._crit_edge.i.i*/
/*   %134 = sdiv i32 %130, 2*/
	main__crit_edgeii_134_reg = main__crit_edgei_35_reg;
end
always @(*) begin
	/* main: %._crit_edge.i.i*/
	/*   %135 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %134*/
		main__crit_edgeii_135 = (`TAG_g_heap_a + (4 * main__crit_edgeii_134));
end
always @(posedge clk) begin
	/* main: %._crit_edge.i.i*/
	/*   %135 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %134*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_226)) begin
		main__crit_edgeii_135_reg <= main__crit_edgeii_135;
		if (start == 1'b0 && ^(main__crit_edgeii_135) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgeii_135_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %._crit_edge.i.i*/
	/*   %136 = load %struct.node** %135, align 4, !tbaa !11*/
		main__crit_edgeii_136 = memory_controller_out_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(posedge clk) begin
	/* main: %._crit_edge.i.i*/
	/*   %136 = load %struct.node** %135, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_228)) begin
		main__crit_edgeii_136_reg <= main__crit_edgeii_136;
		if (start == 1'b0 && ^(main__crit_edgeii_136) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgeii_136_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %._crit_edge.i.i*/
	/*   %137 = getelementptr inbounds %struct.node* %136, i32 0, i32 0*/
		main__crit_edgeii_137 = main__crit_edgeii_136;
end
always @(*) begin
	/* main: %._crit_edge.i.i*/
	/*   %138 = load i32* %137, align 4, !tbaa !7*/
		main__crit_edgeii_138 = memory_controller_out_b[31:0];
end
always @(*) begin
	/* main: %._crit_edge.i.i*/
	/*   %139 = getelementptr inbounds %struct.node* %.pre.i.i, i32 0, i32 0*/
		main__crit_edgeii_139 = main__crit_edgeii_preii;
end
always @(posedge clk) begin
	/* main: %._crit_edge.i.i*/
	/*   %139 = getelementptr inbounds %struct.node* %.pre.i.i, i32 0, i32 0*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_196)) begin
		main__crit_edgeii_139_reg <= main__crit_edgeii_139;
		if (start == 1'b0 && ^(main__crit_edgeii_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgeii_139_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %._crit_edge.i.i*/
	/*   %140 = load i32* %139, align 4, !tbaa !7*/
		main__crit_edgeii_140 = memory_controller_out_a[31:0];
end
always @(posedge clk) begin
	/* main: %._crit_edge.i.i*/
	/*   %140 = load i32* %139, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_229)) begin
		main__crit_edgeii_140_reg <= main__crit_edgeii_140;
		if (start == 1'b0 && ^(main__crit_edgeii_140) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__crit_edgeii_140_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %._crit_edge.i.i*/
	/*   %141 = icmp sgt i32 %138, %140*/
		main__crit_edgeii_141 = ($signed(main__crit_edgeii_138) > $signed(main__crit_edgeii_140_reg));
end
always @(*) begin
	/* main: %insert.exit.i*/
	/*   %142 = icmp sgt i32 %53, 1*/
		main_insertexiti_142 = ($signed(main_lrph14i_53_reg) > $signed(32'd1));
end
always @(*) begin
	/* main: %build_trie.exit*/
	/*   %.lcssa.i = phi i32 [ %heap_size.1, %44 ], [ %53, %build_trie.exit.loopexit ]*/
	if ((((cur_state == LEGUP_F_main_BB__44_100) & (memory_controller_waitrequest == 1'd0)) & (main_44_47 == 1'd0))) begin
		main_build_trieexit_lcssai = main_insertexit_heap_size1_reg;
	end
	/* main: %build_trie.exit*/
	/*   %.lcssa.i = phi i32 [ %heap_size.1, %44 ], [ %53, %build_trie.exit.loopexit ]*/
	else /* if (((cur_state == LEGUP_F_main_BB_build_trieexitloopexit_233) & (memory_controller_waitrequest == 1'd0))) */ begin
		main_build_trieexit_lcssai = main_lrph14i_53_reg;
	end
end
always @(posedge clk) begin
	/* main: %build_trie.exit*/
	/*   %.lcssa.i = phi i32 [ %heap_size.1, %44 ], [ %53, %build_trie.exit.loopexit ]*/
	if ((((cur_state == LEGUP_F_main_BB__44_100) & (memory_controller_waitrequest == 1'd0)) & (main_44_47 == 1'd0))) begin
		main_build_trieexit_lcssai_reg <= main_build_trieexit_lcssai;
		if (start == 1'b0 && ^(main_build_trieexit_lcssai) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_build_trieexit_lcssai_reg"); $finish; end
	end
	/* main: %build_trie.exit*/
	/*   %.lcssa.i = phi i32 [ %heap_size.1, %44 ], [ %53, %build_trie.exit.loopexit ]*/
	if (((cur_state == LEGUP_F_main_BB_build_trieexitloopexit_233) & (memory_controller_waitrequest == 1'd0))) begin
		main_build_trieexit_lcssai_reg <= main_build_trieexit_lcssai;
		if (start == 1'b0 && ^(main_build_trieexit_lcssai) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_build_trieexit_lcssai_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %build_trie.exit*/
	/*   %143 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %.lcssa.i*/
		main_build_trieexit_143 = (`TAG_g_heap_a + (4 * main_build_trieexit_lcssai_reg));
end
always @(posedge clk) begin
	/* main: %build_trie.exit*/
	/*   %143 = getelementptr inbounds [129 x %struct.node*]* @heap, i32 0, i32 %.lcssa.i*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_234)) begin
		main_build_trieexit_143_reg <= main_build_trieexit_143;
		if (start == 1'b0 && ^(main_build_trieexit_143) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_build_trieexit_143_reg"); $finish; end
	end
end
always @(*) begin
	/* main: %build_trie.exit*/
	/*   %144 = load %struct.node** %143, align 4, !tbaa !11*/
		main_build_trieexit_144 = memory_controller_out_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
always @(*) begin
	/* main: %.lr.ph.i.preheader*/
	/*   %23 = sdiv i32 %20, 2*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_20)) begin
		main_signed_divide_32_0_op0 = main_19_20_reg;
	end
	/* main: %._crit_edge.i*/
	/*   %35 = sdiv i32 %31, 2*/
	else if ((cur_state == LEGUP_F_main_BB__crit_edgei_61)) begin
		main_signed_divide_32_0_op0 = main_lrph_31_reg;
	end
	/* main: %.lr.ph.i.preheader.i*/
	/*   %122 = sdiv i32 %53, 2*/
	else if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_153)) begin
		main_signed_divide_32_0_op0 = main_lrph14i_53_reg;
	end
	/* main: %._crit_edge.i.i*/
	/*   %134 = sdiv i32 %130, 2*/
	else /* if ((cur_state == LEGUP_F_main_BB__crit_edgeii_194)) */ begin
		main_signed_divide_32_0_op0 = main_lrphi_130_reg;
	end
end
always @(*) begin
	/* main: %.lr.ph.i.preheader*/
	/*   %23 = sdiv i32 %20, 2*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_20)) begin
		main_signed_divide_32_0_op1 = 32'd2;
	end
	/* main: %._crit_edge.i*/
	/*   %35 = sdiv i32 %31, 2*/
	else if ((cur_state == LEGUP_F_main_BB__crit_edgei_61)) begin
		main_signed_divide_32_0_op1 = 32'd2;
	end
	/* main: %.lr.ph.i.preheader.i*/
	/*   %122 = sdiv i32 %53, 2*/
	else if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_153)) begin
		main_signed_divide_32_0_op1 = 32'd2;
	end
	/* main: %._crit_edge.i.i*/
	/*   %134 = sdiv i32 %130, 2*/
	else /* if ((cur_state == LEGUP_F_main_BB__crit_edgeii_194)) */ begin
		main_signed_divide_32_0_op1 = 32'd2;
	end
end
always @(*) begin
	lpm_divide_main_lrphipreheader_23_en = (memory_controller_waitrequest == 1'd0);
end
always @(*) begin
	lpm_divide_main_lrphipreheader_23_out = lpm_divide_main_lrphipreheader_23_temp_out;
end
always @(*) begin
	main_signed_divide_32_0 = lpm_divide_main_lrphipreheader_23_out;
end
always @(posedge clk) begin
	if ((cur_state == LEGUP_0)) begin
		finish <= 1'd0;
		if (start == 1'b0 && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
	end
	/* main: %build_trie.exit*/
	/*   ret i32 0*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_238)) begin
		finish <= (memory_controller_waitrequest == 1'd0);
		if (start == 1'b0 && ^((memory_controller_waitrequest == 1'd0)) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
	end
end
always @(*) begin
	memory_controller_enable_a = 1'd0;
	if ((cur_state == LEGUP_0)) begin
		memory_controller_enable_a = 1'd0;
	end
	/* main: %1*/
	/*   store i8 %2, i8* %scevgep10, align 4, !tbaa !1*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %1*/
	/*   store %struct.node* null, %struct.node** %scevgep7, align 4, !tbaa !8*/
	if ((cur_state == LEGUP_F_main_BB__1_2)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %6*/
	/*   %10 = load i32* %9, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__6_7)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %6*/
	/*   store i32 %11, i32* %9, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__6_9)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %.lr.ph.i.preheader*/
	/*   %25 = load %struct.node** %24, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_52)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %.lr.ph.i.preheader*/
	/*   %27 = load i32* %26, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_54)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %.lr.ph*/
	/*   store %struct.node* %29, %struct.node** %33, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph_59)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %._crit_edge.i*/
	/*   %41 = load i32* %40, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_94)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %.lr.ph14.i*/
	/*   %50 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %.lr.ph14.i*/
	/*   store %struct.node* %52, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_104)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %56*/
	/*   %58 = load %struct.node** %57, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__56_109)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %56*/
	/*   %60 = load i32* %59, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__56_111)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %67*/
	/*   %69 = load %struct.node** %68, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__67_114)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %67*/
	/*   %71 = load i32* %70, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__67_116)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %77*/
	/*   store %struct.node* %73, %struct.node** %68, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__77_120)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %get_min.exit.i*/
	/*   %81 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* %50, %struct.node** %80, align 4, !tbaa !8*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_124)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %87*/
	/*   %89 = load %struct.node** %88, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__87_130)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %87*/
	/*   %91 = load i32* %90, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__87_132)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %98*/
	/*   %100 = load %struct.node** %99, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__98_135)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %98*/
	/*   %102 = load i32* %101, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__98_137)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %108*/
	/*   store %struct.node* %104, %struct.node** %99, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__108_141)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %get_min.exit12.i*/
	/*   store %struct.node* %81, %struct.node** %111, align 4, !tbaa !9*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_144)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %get_min.exit12.i*/
	/*   %113 = load i32* %112, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_145)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %.lr.ph.i.preheader.i*/
	/*   %124 = load %struct.node** %123, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_185)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %.lr.ph.i.preheader.i*/
	/*   %126 = load i32* %125, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_187)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %.lr.ph.i*/
	/*   store %struct.node* %128, %struct.node** %132, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_192)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %._crit_edge.i.i*/
	/*   %140 = load i32* %139, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_227)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %build_trie.exit*/
	/*   %144 = load %struct.node** %143, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_234)) begin
		memory_controller_enable_a = 1'd1;
	end
	/* main: %build_trie.exit*/
	/*   store %struct.node* null, %struct.node** %143, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_237)) begin
		memory_controller_enable_a = 1'd1;
	end
end
always @(*) begin
	memory_controller_address_a = 1'd0;
	if ((cur_state == LEGUP_0)) begin
		memory_controller_address_a = 1'd0;
	end
	/* main: %1*/
	/*   store i8 %2, i8* %scevgep10, align 4, !tbaa !1*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		memory_controller_address_a = main_1_scevgep10;
	end
	/* main: %1*/
	/*   store %struct.node* null, %struct.node** %scevgep7, align 4, !tbaa !8*/
	if ((cur_state == LEGUP_F_main_BB__1_2)) begin
		memory_controller_address_a = main_1_scevgep7_reg;
	end
	/* main: %6*/
	/*   %10 = load i32* %9, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__6_7)) begin
		memory_controller_address_a = main_6_9;
	end
	/* main: %6*/
	/*   store i32 %11, i32* %9, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__6_9)) begin
		memory_controller_address_a = main_6_9_reg;
	end
	/* main: %.lr.ph.i.preheader*/
	/*   %25 = load %struct.node** %24, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_52)) begin
		memory_controller_address_a = main_lrphipreheader_24;
	end
	/* main: %.lr.ph.i.preheader*/
	/*   %27 = load i32* %26, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_54)) begin
		memory_controller_address_a = main_lrphipreheader_26;
	end
	/* main: %.lr.ph*/
	/*   store %struct.node* %29, %struct.node** %33, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph_59)) begin
		memory_controller_address_a = main_lrph_33_reg;
	end
	/* main: %._crit_edge.i*/
	/*   %41 = load i32* %40, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_94)) begin
		memory_controller_address_a = main__crit_edgei_40_reg;
	end
	/* main: %.lr.ph14.i*/
	/*   %50 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		memory_controller_address_a = (`TAG_g_heap_a + (4 * 32'd1));
	end
	/* main: %.lr.ph14.i*/
	/*   store %struct.node* %52, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_104)) begin
		memory_controller_address_a = (`TAG_g_heap_a + (4 * 32'd1));
	end
	/* main: %56*/
	/*   %58 = load %struct.node** %57, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__56_109)) begin
		memory_controller_address_a = main_56_57;
	end
	/* main: %56*/
	/*   %60 = load i32* %59, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__56_111)) begin
		memory_controller_address_a = main_56_59;
	end
	/* main: %67*/
	/*   %69 = load %struct.node** %68, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__67_114)) begin
		memory_controller_address_a = main_67_68;
	end
	/* main: %67*/
	/*   %71 = load i32* %70, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__67_116)) begin
		memory_controller_address_a = main_67_70;
	end
	/* main: %77*/
	/*   store %struct.node* %73, %struct.node** %68, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__77_120)) begin
		memory_controller_address_a = main_67_68_reg;
	end
	/* main: %get_min.exit.i*/
	/*   %81 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		memory_controller_address_a = (`TAG_g_heap_a + (4 * 32'd1));
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* %50, %struct.node** %80, align 4, !tbaa !8*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_124)) begin
		memory_controller_address_a = main_get_minexiti_80_reg;
	end
	/* main: %87*/
	/*   %89 = load %struct.node** %88, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__87_130)) begin
		memory_controller_address_a = main_87_88;
	end
	/* main: %87*/
	/*   %91 = load i32* %90, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__87_132)) begin
		memory_controller_address_a = main_87_90;
	end
	/* main: %98*/
	/*   %100 = load %struct.node** %99, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__98_135)) begin
		memory_controller_address_a = main_98_99;
	end
	/* main: %98*/
	/*   %102 = load i32* %101, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__98_137)) begin
		memory_controller_address_a = main_98_101;
	end
	/* main: %108*/
	/*   store %struct.node* %104, %struct.node** %99, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__108_141)) begin
		memory_controller_address_a = main_98_99_reg;
	end
	/* main: %get_min.exit12.i*/
	/*   store %struct.node* %81, %struct.node** %111, align 4, !tbaa !9*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_144)) begin
		memory_controller_address_a = main_get_minexit12i_111;
	end
	/* main: %get_min.exit12.i*/
	/*   %113 = load i32* %112, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_145)) begin
		memory_controller_address_a = main_get_minexit12i_112_reg;
	end
	/* main: %.lr.ph.i.preheader.i*/
	/*   %124 = load %struct.node** %123, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_185)) begin
		memory_controller_address_a = main_lrphipreheaderi_123;
	end
	/* main: %.lr.ph.i.preheader.i*/
	/*   %126 = load i32* %125, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_187)) begin
		memory_controller_address_a = main_lrphipreheaderi_125;
	end
	/* main: %.lr.ph.i*/
	/*   store %struct.node* %128, %struct.node** %132, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_192)) begin
		memory_controller_address_a = main_lrphi_132_reg;
	end
	/* main: %._crit_edge.i.i*/
	/*   %140 = load i32* %139, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_227)) begin
		memory_controller_address_a = main__crit_edgeii_139_reg;
	end
	/* main: %build_trie.exit*/
	/*   %144 = load %struct.node** %143, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_234)) begin
		memory_controller_address_a = main_build_trieexit_143;
	end
	/* main: %build_trie.exit*/
	/*   store %struct.node* null, %struct.node** %143, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_237)) begin
		memory_controller_address_a = main_build_trieexit_143_reg;
	end
end
always @(*) begin
	memory_controller_write_enable_a = 1'd0;
	if ((cur_state == LEGUP_0)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %1*/
	/*   store i8 %2, i8* %scevgep10, align 4, !tbaa !1*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		memory_controller_write_enable_a = 1'd1;
	end
	/* main: %1*/
	/*   store %struct.node* null, %struct.node** %scevgep7, align 4, !tbaa !8*/
	if ((cur_state == LEGUP_F_main_BB__1_2)) begin
		memory_controller_write_enable_a = 1'd1;
	end
	/* main: %6*/
	/*   %10 = load i32* %9, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__6_7)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %6*/
	/*   store i32 %11, i32* %9, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__6_9)) begin
		memory_controller_write_enable_a = 1'd1;
	end
	/* main: %.lr.ph.i.preheader*/
	/*   %25 = load %struct.node** %24, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_52)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %.lr.ph.i.preheader*/
	/*   %27 = load i32* %26, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_54)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %.lr.ph*/
	/*   store %struct.node* %29, %struct.node** %33, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph_59)) begin
		memory_controller_write_enable_a = 1'd1;
	end
	/* main: %._crit_edge.i*/
	/*   %41 = load i32* %40, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_94)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %.lr.ph14.i*/
	/*   %50 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %.lr.ph14.i*/
	/*   store %struct.node* %52, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_104)) begin
		memory_controller_write_enable_a = 1'd1;
	end
	/* main: %56*/
	/*   %58 = load %struct.node** %57, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__56_109)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %56*/
	/*   %60 = load i32* %59, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__56_111)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %67*/
	/*   %69 = load %struct.node** %68, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__67_114)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %67*/
	/*   %71 = load i32* %70, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__67_116)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %77*/
	/*   store %struct.node* %73, %struct.node** %68, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__77_120)) begin
		memory_controller_write_enable_a = 1'd1;
	end
	/* main: %get_min.exit.i*/
	/*   %81 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* %50, %struct.node** %80, align 4, !tbaa !8*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_124)) begin
		memory_controller_write_enable_a = 1'd1;
	end
	/* main: %87*/
	/*   %89 = load %struct.node** %88, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__87_130)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %87*/
	/*   %91 = load i32* %90, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__87_132)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %98*/
	/*   %100 = load %struct.node** %99, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__98_135)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %98*/
	/*   %102 = load i32* %101, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__98_137)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %108*/
	/*   store %struct.node* %104, %struct.node** %99, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__108_141)) begin
		memory_controller_write_enable_a = 1'd1;
	end
	/* main: %get_min.exit12.i*/
	/*   store %struct.node* %81, %struct.node** %111, align 4, !tbaa !9*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_144)) begin
		memory_controller_write_enable_a = 1'd1;
	end
	/* main: %get_min.exit12.i*/
	/*   %113 = load i32* %112, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_145)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %.lr.ph.i.preheader.i*/
	/*   %124 = load %struct.node** %123, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_185)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %.lr.ph.i.preheader.i*/
	/*   %126 = load i32* %125, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_187)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %.lr.ph.i*/
	/*   store %struct.node* %128, %struct.node** %132, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_192)) begin
		memory_controller_write_enable_a = 1'd1;
	end
	/* main: %._crit_edge.i.i*/
	/*   %140 = load i32* %139, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_227)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %build_trie.exit*/
	/*   %144 = load %struct.node** %143, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_234)) begin
		memory_controller_write_enable_a = 1'd0;
	end
	/* main: %build_trie.exit*/
	/*   store %struct.node* null, %struct.node** %143, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_237)) begin
		memory_controller_write_enable_a = 1'd1;
	end
end
always @(*) begin
	memory_controller_in_a = 1'd0;
	if ((cur_state == LEGUP_0)) begin
		memory_controller_in_a = 1'd0;
	end
	/* main: %1*/
	/*   store i8 %2, i8* %scevgep10, align 4, !tbaa !1*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		memory_controller_in_a = main_1_2;
	end
	/* main: %1*/
	/*   store %struct.node* null, %struct.node** %scevgep7, align 4, !tbaa !8*/
	if ((cur_state == LEGUP_F_main_BB__1_2)) begin
		memory_controller_in_a = 0;
	end
	/* main: %6*/
	/*   store i32 %11, i32* %9, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__6_9)) begin
		memory_controller_in_a = main_6_11;
	end
	/* main: %.lr.ph*/
	/*   store %struct.node* %29, %struct.node** %33, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph_59)) begin
		memory_controller_in_a = main_lrph_29_reg;
	end
	/* main: %.lr.ph14.i*/
	/*   store %struct.node* %52, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_104)) begin
		memory_controller_in_a = main_lrph14i_52;
	end
	/* main: %77*/
	/*   store %struct.node* %73, %struct.node** %68, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__77_120)) begin
		memory_controller_in_a = main_67_73_reg;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* %50, %struct.node** %80, align 4, !tbaa !8*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_124)) begin
		memory_controller_in_a = main_lrph14i_50_reg;
	end
	/* main: %108*/
	/*   store %struct.node* %104, %struct.node** %99, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__108_141)) begin
		memory_controller_in_a = main_98_104_reg;
	end
	/* main: %get_min.exit12.i*/
	/*   store %struct.node* %81, %struct.node** %111, align 4, !tbaa !9*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_144)) begin
		memory_controller_in_a = main_get_minexiti_81_reg;
	end
	/* main: %.lr.ph.i*/
	/*   store %struct.node* %128, %struct.node** %132, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_192)) begin
		memory_controller_in_a = main_lrphi_128_reg;
	end
	/* main: %build_trie.exit*/
	/*   store %struct.node* null, %struct.node** %143, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_237)) begin
		memory_controller_in_a = 0;
	end
end
always @(*) begin
	memory_controller_size_a = 1'd0;
	if ((cur_state == LEGUP_0)) begin
		memory_controller_size_a = 1'd0;
	end
	/* main: %1*/
	/*   store i8 %2, i8* %scevgep10, align 4, !tbaa !1*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		memory_controller_size_a = 2'd0;
	end
	/* main: %1*/
	/*   store %struct.node* null, %struct.node** %scevgep7, align 4, !tbaa !8*/
	if ((cur_state == LEGUP_F_main_BB__1_2)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %6*/
	/*   %10 = load i32* %9, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__6_7)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %6*/
	/*   store i32 %11, i32* %9, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__6_9)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %.lr.ph.i.preheader*/
	/*   %25 = load %struct.node** %24, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_52)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %.lr.ph.i.preheader*/
	/*   %27 = load i32* %26, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheader_54)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %.lr.ph*/
	/*   store %struct.node* %29, %struct.node** %33, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph_59)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %._crit_edge.i*/
	/*   %41 = load i32* %40, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_94)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %.lr.ph14.i*/
	/*   %50 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %.lr.ph14.i*/
	/*   store %struct.node* %52, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_104)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %56*/
	/*   %58 = load %struct.node** %57, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__56_109)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %56*/
	/*   %60 = load i32* %59, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__56_111)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %67*/
	/*   %69 = load %struct.node** %68, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__67_114)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %67*/
	/*   %71 = load i32* %70, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__67_116)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %77*/
	/*   store %struct.node* %73, %struct.node** %68, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__77_120)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %get_min.exit.i*/
	/*   %81 = load %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* %50, %struct.node** %80, align 4, !tbaa !8*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_124)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %87*/
	/*   %89 = load %struct.node** %88, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__87_130)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %87*/
	/*   %91 = load i32* %90, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__87_132)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %98*/
	/*   %100 = load %struct.node** %99, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__98_135)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %98*/
	/*   %102 = load i32* %101, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__98_137)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %108*/
	/*   store %struct.node* %104, %struct.node** %99, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__108_141)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %get_min.exit12.i*/
	/*   store %struct.node* %81, %struct.node** %111, align 4, !tbaa !9*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_144)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %get_min.exit12.i*/
	/*   %113 = load i32* %112, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_145)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %.lr.ph.i.preheader.i*/
	/*   %124 = load %struct.node** %123, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_185)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %.lr.ph.i.preheader.i*/
	/*   %126 = load i32* %125, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_lrphipreheaderi_187)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %.lr.ph.i*/
	/*   store %struct.node* %128, %struct.node** %132, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_192)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %._crit_edge.i.i*/
	/*   %140 = load i32* %139, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_227)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %build_trie.exit*/
	/*   %144 = load %struct.node** %143, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_234)) begin
		memory_controller_size_a = 2'd2;
	end
	/* main: %build_trie.exit*/
	/*   store %struct.node* null, %struct.node** %143, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_237)) begin
		memory_controller_size_a = 2'd2;
	end
end
always @(*) begin
	memory_controller_enable_b = 1'd0;
	if ((cur_state == LEGUP_0)) begin
		memory_controller_enable_b = 1'd0;
	end
	/* main: %1*/
	/*   store i32 0, i32* %scevgep89, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %1*/
	/*   store %struct.node* null, %struct.node** %scevgep6, align 4, !tbaa !9*/
	if ((cur_state == LEGUP_F_main_BB__1_2)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %6*/
	/*   %7 = load i8* %scevgep4, align 1, !tbaa !10*/
	if ((cur_state == LEGUP_F_main_BB__6_5)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %count_frequencies.exit.preheader*/
	/*   %13 = load i32* %scevgep3, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheader_12)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %19*/
	/*   store %struct.node* %scevgep, %struct.node** %21, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__19_18)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %.lr.ph*/
	/*   store %struct.node* %32, %struct.node** %30, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph_58)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %._crit_edge.i*/
	/*   %.pre.i = load %struct.node** %30, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_61)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %._crit_edge.i*/
	/*   %37 = load %struct.node** %36, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_93)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %._crit_edge.i*/
	/*   %39 = load i32* %38, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_95)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %.lr.ph14.i*/
	/*   %52 = load %struct.node** %51, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %.lr.ph14.i*/
	/*   store %struct.node* null, %struct.node** %51, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_105)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %56*/
	/*   %63 = load %struct.node** %62, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__56_109)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %56*/
	/*   %65 = load i32* %64, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__56_111)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %67*/
	/*   %73 = load %struct.node** %72, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__67_114)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %67*/
	/*   %75 = load i32* %74, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__67_116)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %77*/
	/*   store %struct.node* %69, %struct.node** %72, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__77_119)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %get_min.exit.i*/
	/*   %83 = load %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* %83, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_125)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* null, %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_126)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %87*/
	/*   %94 = load %struct.node** %93, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__87_130)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %87*/
	/*   %96 = load i32* %95, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__87_132)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %98*/
	/*   %104 = load %struct.node** %103, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__98_135)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %98*/
	/*   %106 = load i32* %105, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__98_137)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %108*/
	/*   store %struct.node* %100, %struct.node** %103, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__108_140)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %get_min.exit12.i*/
	/*   %115 = load i32* %114, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_145)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %get_min.exit12.i*/
	/*   store i32 %116, i32* %117, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_147)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %120*/
	/*   store %struct.node* %49, %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__120_151)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %.lr.ph.i*/
	/*   store %struct.node* %131, %struct.node** %129, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_191)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %._crit_edge.i.i*/
	/*   %.pre.i.i = load %struct.node** %129, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_194)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %._crit_edge.i.i*/
	/*   %136 = load %struct.node** %135, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_226)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %._crit_edge.i.i*/
	/*   %138 = load i32* %137, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_228)) begin
		memory_controller_enable_b = 1'd1;
	end
	/* main: %build_trie.exit*/
	/*   store %struct.node* %144, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_236)) begin
		memory_controller_enable_b = 1'd1;
	end
end
always @(*) begin
	memory_controller_address_b = 1'd0;
	if ((cur_state == LEGUP_0)) begin
		memory_controller_address_b = 1'd0;
	end
	/* main: %1*/
	/*   store i32 0, i32* %scevgep89, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		memory_controller_address_b = main_1_scevgep89;
	end
	/* main: %1*/
	/*   store %struct.node* null, %struct.node** %scevgep6, align 4, !tbaa !9*/
	if ((cur_state == LEGUP_F_main_BB__1_2)) begin
		memory_controller_address_b = main_1_scevgep6_reg;
	end
	/* main: %6*/
	/*   %7 = load i8* %scevgep4, align 1, !tbaa !10*/
	if ((cur_state == LEGUP_F_main_BB__6_5)) begin
		memory_controller_address_b = main_6_scevgep4;
	end
	/* main: %count_frequencies.exit.preheader*/
	/*   %13 = load i32* %scevgep3, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheader_12)) begin
		memory_controller_address_b = main_count_frequenciesexitpreheader_scevgep3;
	end
	/* main: %19*/
	/*   store %struct.node* %scevgep, %struct.node** %21, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__19_18)) begin
		memory_controller_address_b = main_19_21;
	end
	/* main: %.lr.ph*/
	/*   store %struct.node* %32, %struct.node** %30, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph_58)) begin
		memory_controller_address_b = main_lrph_30_reg;
	end
	/* main: %._crit_edge.i*/
	/*   %.pre.i = load %struct.node** %30, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_61)) begin
		memory_controller_address_b = main_lrph_30_reg;
	end
	/* main: %._crit_edge.i*/
	/*   %37 = load %struct.node** %36, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_93)) begin
		memory_controller_address_b = main__crit_edgei_36;
	end
	/* main: %._crit_edge.i*/
	/*   %39 = load i32* %38, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_95)) begin
		memory_controller_address_b = main__crit_edgei_38;
	end
	/* main: %.lr.ph14.i*/
	/*   %52 = load %struct.node** %51, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		memory_controller_address_b = main_lrph14i_51;
	end
	/* main: %.lr.ph14.i*/
	/*   store %struct.node* null, %struct.node** %51, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_105)) begin
		memory_controller_address_b = main_lrph14i_51_reg;
	end
	/* main: %56*/
	/*   %63 = load %struct.node** %62, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__56_109)) begin
		memory_controller_address_b = main_56_62;
	end
	/* main: %56*/
	/*   %65 = load i32* %64, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__56_111)) begin
		memory_controller_address_b = main_56_64;
	end
	/* main: %67*/
	/*   %73 = load %struct.node** %72, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__67_114)) begin
		memory_controller_address_b = main_67_72;
	end
	/* main: %67*/
	/*   %75 = load i32* %74, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__67_116)) begin
		memory_controller_address_b = main_67_74;
	end
	/* main: %77*/
	/*   store %struct.node* %69, %struct.node** %72, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__77_119)) begin
		memory_controller_address_b = main_67_72_reg;
	end
	/* main: %get_min.exit.i*/
	/*   %83 = load %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		memory_controller_address_b = main_get_minexiti_82;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* %83, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_125)) begin
		memory_controller_address_b = (`TAG_g_heap_a + (4 * 32'd1));
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* null, %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_126)) begin
		memory_controller_address_b = main_get_minexiti_82_reg;
	end
	/* main: %87*/
	/*   %94 = load %struct.node** %93, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__87_130)) begin
		memory_controller_address_b = main_87_93;
	end
	/* main: %87*/
	/*   %96 = load i32* %95, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__87_132)) begin
		memory_controller_address_b = main_87_95;
	end
	/* main: %98*/
	/*   %104 = load %struct.node** %103, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__98_135)) begin
		memory_controller_address_b = main_98_103;
	end
	/* main: %98*/
	/*   %106 = load i32* %105, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__98_137)) begin
		memory_controller_address_b = main_98_105;
	end
	/* main: %108*/
	/*   store %struct.node* %100, %struct.node** %103, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__108_140)) begin
		memory_controller_address_b = main_98_103_reg;
	end
	/* main: %get_min.exit12.i*/
	/*   %115 = load i32* %114, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_145)) begin
		memory_controller_address_b = main_get_minexit12i_114_reg;
	end
	/* main: %get_min.exit12.i*/
	/*   store i32 %116, i32* %117, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_147)) begin
		memory_controller_address_b = main_get_minexit12i_117_reg;
	end
	/* main: %120*/
	/*   store %struct.node* %49, %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__120_151)) begin
		memory_controller_address_b = main_get_minexiti_82_reg;
	end
	/* main: %.lr.ph.i*/
	/*   store %struct.node* %131, %struct.node** %129, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_191)) begin
		memory_controller_address_b = main_lrphi_129_reg;
	end
	/* main: %._crit_edge.i.i*/
	/*   %.pre.i.i = load %struct.node** %129, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_194)) begin
		memory_controller_address_b = main_lrphi_129_reg;
	end
	/* main: %._crit_edge.i.i*/
	/*   %136 = load %struct.node** %135, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_226)) begin
		memory_controller_address_b = main__crit_edgeii_135;
	end
	/* main: %._crit_edge.i.i*/
	/*   %138 = load i32* %137, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_228)) begin
		memory_controller_address_b = main__crit_edgeii_137;
	end
	/* main: %build_trie.exit*/
	/*   store %struct.node* %144, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_236)) begin
		memory_controller_address_b = (`TAG_g_heap_a + (4 * 32'd1));
	end
end
always @(*) begin
	memory_controller_write_enable_b = 1'd0;
	if ((cur_state == LEGUP_0)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %1*/
	/*   store i32 0, i32* %scevgep89, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %1*/
	/*   store %struct.node* null, %struct.node** %scevgep6, align 4, !tbaa !9*/
	if ((cur_state == LEGUP_F_main_BB__1_2)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %6*/
	/*   %7 = load i8* %scevgep4, align 1, !tbaa !10*/
	if ((cur_state == LEGUP_F_main_BB__6_5)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %count_frequencies.exit.preheader*/
	/*   %13 = load i32* %scevgep3, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheader_12)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %19*/
	/*   store %struct.node* %scevgep, %struct.node** %21, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__19_18)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %.lr.ph*/
	/*   store %struct.node* %32, %struct.node** %30, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph_58)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %._crit_edge.i*/
	/*   %.pre.i = load %struct.node** %30, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_61)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %._crit_edge.i*/
	/*   %37 = load %struct.node** %36, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_93)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %._crit_edge.i*/
	/*   %39 = load i32* %38, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_95)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %.lr.ph14.i*/
	/*   %52 = load %struct.node** %51, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %.lr.ph14.i*/
	/*   store %struct.node* null, %struct.node** %51, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_105)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %56*/
	/*   %63 = load %struct.node** %62, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__56_109)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %56*/
	/*   %65 = load i32* %64, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__56_111)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %67*/
	/*   %73 = load %struct.node** %72, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__67_114)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %67*/
	/*   %75 = load i32* %74, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__67_116)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %77*/
	/*   store %struct.node* %69, %struct.node** %72, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__77_119)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %get_min.exit.i*/
	/*   %83 = load %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* %83, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_125)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* null, %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_126)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %87*/
	/*   %94 = load %struct.node** %93, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__87_130)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %87*/
	/*   %96 = load i32* %95, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__87_132)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %98*/
	/*   %104 = load %struct.node** %103, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__98_135)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %98*/
	/*   %106 = load i32* %105, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__98_137)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %108*/
	/*   store %struct.node* %100, %struct.node** %103, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__108_140)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %get_min.exit12.i*/
	/*   %115 = load i32* %114, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_145)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %get_min.exit12.i*/
	/*   store i32 %116, i32* %117, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_147)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %120*/
	/*   store %struct.node* %49, %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__120_151)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %.lr.ph.i*/
	/*   store %struct.node* %131, %struct.node** %129, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_191)) begin
		memory_controller_write_enable_b = 1'd1;
	end
	/* main: %._crit_edge.i.i*/
	/*   %.pre.i.i = load %struct.node** %129, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_194)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %._crit_edge.i.i*/
	/*   %136 = load %struct.node** %135, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_226)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %._crit_edge.i.i*/
	/*   %138 = load i32* %137, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_228)) begin
		memory_controller_write_enable_b = 1'd0;
	end
	/* main: %build_trie.exit*/
	/*   store %struct.node* %144, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_236)) begin
		memory_controller_write_enable_b = 1'd1;
	end
end
always @(*) begin
	memory_controller_in_b = 1'd0;
	if ((cur_state == LEGUP_0)) begin
		memory_controller_in_b = 1'd0;
	end
	/* main: %1*/
	/*   store i32 0, i32* %scevgep89, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		memory_controller_in_b = 32'd0;
	end
	/* main: %1*/
	/*   store %struct.node* null, %struct.node** %scevgep6, align 4, !tbaa !9*/
	if ((cur_state == LEGUP_F_main_BB__1_2)) begin
		memory_controller_in_b = 0;
	end
	/* main: %19*/
	/*   store %struct.node* %scevgep, %struct.node** %21, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__19_18)) begin
		memory_controller_in_b = main_count_frequenciesexitpreheader_scevgep_reg;
	end
	/* main: %.lr.ph*/
	/*   store %struct.node* %32, %struct.node** %30, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph_58)) begin
		memory_controller_in_b = main_lrph_32_reg;
	end
	/* main: %.lr.ph14.i*/
	/*   store %struct.node* null, %struct.node** %51, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_105)) begin
		memory_controller_in_b = 0;
	end
	/* main: %77*/
	/*   store %struct.node* %69, %struct.node** %72, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__77_119)) begin
		memory_controller_in_b = main_67_69_reg;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* %83, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_125)) begin
		memory_controller_in_b = main_get_minexiti_83;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* null, %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_126)) begin
		memory_controller_in_b = 0;
	end
	/* main: %108*/
	/*   store %struct.node* %100, %struct.node** %103, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__108_140)) begin
		memory_controller_in_b = main_98_100_reg;
	end
	/* main: %get_min.exit12.i*/
	/*   store i32 %116, i32* %117, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_147)) begin
		memory_controller_in_b = main_get_minexit12i_116;
	end
	/* main: %120*/
	/*   store %struct.node* %49, %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__120_151)) begin
		memory_controller_in_b = main_lrph14i_49_reg;
	end
	/* main: %.lr.ph.i*/
	/*   store %struct.node* %131, %struct.node** %129, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_191)) begin
		memory_controller_in_b = main_lrphi_131_reg;
	end
	/* main: %build_trie.exit*/
	/*   store %struct.node* %144, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_236)) begin
		memory_controller_in_b = main_build_trieexit_144;
	end
end
always @(*) begin
	memory_controller_size_b = 1'd0;
	if ((cur_state == LEGUP_0)) begin
		memory_controller_size_b = 1'd0;
	end
	/* main: %1*/
	/*   store i32 0, i32* %scevgep89, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__1_1)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %1*/
	/*   store %struct.node* null, %struct.node** %scevgep6, align 4, !tbaa !9*/
	if ((cur_state == LEGUP_F_main_BB__1_2)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %6*/
	/*   %7 = load i8* %scevgep4, align 1, !tbaa !10*/
	if ((cur_state == LEGUP_F_main_BB__6_5)) begin
		memory_controller_size_b = 2'd0;
	end
	/* main: %count_frequencies.exit.preheader*/
	/*   %13 = load i32* %scevgep3, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_count_frequenciesexitpreheader_12)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %19*/
	/*   store %struct.node* %scevgep, %struct.node** %21, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__19_18)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %.lr.ph*/
	/*   store %struct.node* %32, %struct.node** %30, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph_58)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %._crit_edge.i*/
	/*   %.pre.i = load %struct.node** %30, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_61)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %._crit_edge.i*/
	/*   %37 = load %struct.node** %36, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_93)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %._crit_edge.i*/
	/*   %39 = load i32* %38, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgei_95)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %.lr.ph14.i*/
	/*   %52 = load %struct.node** %51, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_102)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %.lr.ph14.i*/
	/*   store %struct.node* null, %struct.node** %51, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrph14i_105)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %56*/
	/*   %63 = load %struct.node** %62, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__56_109)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %56*/
	/*   %65 = load i32* %64, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__56_111)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %67*/
	/*   %73 = load %struct.node** %72, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__67_114)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %67*/
	/*   %75 = load i32* %74, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__67_116)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %77*/
	/*   store %struct.node* %69, %struct.node** %72, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__77_119)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %get_min.exit.i*/
	/*   %83 = load %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_123)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* %83, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_125)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %get_min.exit.i*/
	/*   store %struct.node* null, %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_get_minexiti_126)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %87*/
	/*   %94 = load %struct.node** %93, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__87_130)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %87*/
	/*   %96 = load i32* %95, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__87_132)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %98*/
	/*   %104 = load %struct.node** %103, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__98_135)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %98*/
	/*   %106 = load i32* %105, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__98_137)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %108*/
	/*   store %struct.node* %100, %struct.node** %103, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__108_140)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %get_min.exit12.i*/
	/*   %115 = load i32* %114, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_145)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %get_min.exit12.i*/
	/*   store i32 %116, i32* %117, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB_get_minexit12i_147)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %120*/
	/*   store %struct.node* %49, %struct.node** %82, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__120_151)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %.lr.ph.i*/
	/*   store %struct.node* %131, %struct.node** %129, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_lrphi_191)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %._crit_edge.i.i*/
	/*   %.pre.i.i = load %struct.node** %129, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_194)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %._crit_edge.i.i*/
	/*   %136 = load %struct.node** %135, align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_226)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %._crit_edge.i.i*/
	/*   %138 = load i32* %137, align 4, !tbaa !7*/
	if ((cur_state == LEGUP_F_main_BB__crit_edgeii_228)) begin
		memory_controller_size_b = 2'd2;
	end
	/* main: %build_trie.exit*/
	/*   store %struct.node* %144, %struct.node** getelementptr inbounds ([129 x %struct.node*]* @heap, i32 0, i32 1), align 4, !tbaa !11*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_236)) begin
		memory_controller_size_b = 2'd2;
	end
end
always @(posedge clk) begin
	if ((cur_state == LEGUP_0)) begin
		return_val <= 0;
		if (start == 1'b0 && ^(0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
	end
	/* main: %build_trie.exit*/
	/*   ret i32 0*/
	if ((cur_state == LEGUP_F_main_BB_build_trieexit_238)) begin
		return_val <= 32'd0;
		if (start == 1'b0 && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
	end
end

endmodule 
`timescale 1 ns / 1 ns
module ram_dual_port
(
	clk,
	clken,
	address_a,
	address_b,
	q_a,
	q_b,
	wren_a,
	wren_b,
	data_a,
	data_b,
	byteena_a,
	byteena_b
);

parameter  width_a = 1'd0;
parameter  width_b = 1'd0;
parameter  widthad_a = 1'd0;
parameter  widthad_b = 1'd0;
parameter  numwords_a = 1'd0;
parameter  numwords_b = 1'd0;
parameter  latency = 1'd1;
parameter  init_file = "UNUSED";
parameter  width_be_a = 1'd0;
parameter  width_be_b = 1'd0;

input  clk;
input  clken;
input [(widthad_a-1):0] address_a;
input [(widthad_b-1):0] address_b;
output [(width_a-1):0] q_a;
output [(width_b-1):0] q_b;
input  wren_a;
input  wren_b;
input [(width_a-1):0] data_a;
input [(width_b-1):0] data_b;
input [width_be_a-1:0] byteena_a;
input [width_be_b-1:0] byteena_b;
wire [(width_a-1):0] q_a_wire;
wire [(width_b-1):0] q_b_wire;
reg  clk_wire;


altsyncram altsyncram_component (
	.clock0 (clk_wire),
	.clock1 (1'd1),
	.clocken0 (clken),
	.clocken1 (1'd1),
	.clocken2 (1'd1),
	.clocken3 (1'd1),
	.aclr0 (1'd0),
	.aclr1 (1'd0),
	.addressstall_a (1'd0),
	.addressstall_b (1'd0),
	.eccstatus (),
	.address_a (address_a),
	.address_b (address_b),
	.rden_a (clken),
	.rden_b (clken),
	.q_a (q_a_wire),
	.q_b (q_b_wire),
	.byteena_a (byteena_a),
	.byteena_b (byteena_b),
	.wren_a (wren_a),
	.wren_b (wren_b),
	.data_a (data_a),
	.data_b (data_b)
);

defparam
	altsyncram_component.width_byteena_a = width_be_a,
	altsyncram_component.width_byteena_b = width_be_b,
	altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
	altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
	altsyncram_component.init_file = init_file,
	altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
	altsyncram_component.lpm_type = "altsyncram",
	altsyncram_component.power_up_uninitialized = "FALSE",
	altsyncram_component.intended_device_family = "Cyclone V",
	altsyncram_component.clock_enable_input_a = "BYPASS",
	altsyncram_component.clock_enable_input_b = "BYPASS",
	altsyncram_component.clock_enable_output_a = "BYPASS",
	altsyncram_component.clock_enable_output_b = "BYPASS",
	altsyncram_component.outdata_aclr_a = "NONE",
	altsyncram_component.outdata_aclr_b = "NONE",
	altsyncram_component.outdata_reg_a = "UNREGISTERED",
	altsyncram_component.outdata_reg_b = "UNREGISTERED",
	altsyncram_component.numwords_a = numwords_a,
	altsyncram_component.numwords_b = numwords_b,
	altsyncram_component.widthad_a = widthad_a,
	altsyncram_component.widthad_b = widthad_b,
	altsyncram_component.width_a = width_a,
	altsyncram_component.width_b = width_b,
	altsyncram_component.address_reg_b = "CLOCK0",
	altsyncram_component.byteena_reg_b = "CLOCK0",
	altsyncram_component.indata_reg_b = "CLOCK0",
	altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";


always @(*) begin
	clk_wire = clk;
end


integer j;
reg [(width_a-1):0] q_a_reg[latency:1], q_b_reg[latency:1];

always @(*)
begin
   q_a_reg[1] <= q_a_wire;
   q_b_reg[1] <= q_b_wire;
end

always @(posedge clk)
if (clken)
begin
   for (j = 1; j < latency; j=j+1)
   begin
       q_a_reg[j+1] <= q_a_reg[j];
       q_b_reg[j+1] <= q_b_reg[j];
   end
end

assign q_a = (clken) ? q_a_reg[latency] : 0;
assign q_b = (clken) ? q_b_reg[latency] : 0;

endmodule 
`timescale 1 ns / 1 ns
module rom_dual_port
(
	clk,
	clken,
	address_a,
	address_b,
	q_a,
	q_b
);

parameter  width_a = 1'd0;
parameter  width_b = 1'd0;
parameter  widthad_a = 1'd0;
parameter  widthad_b = 1'd0;
parameter  numwords_a = 1'd0;
parameter  numwords_b = 1'd0;
parameter  latency = 1'd1;
parameter  init_file = "UNUSED";

input  clk;
input  clken;
input [(widthad_a-1):0] address_a;
input [(widthad_b-1):0] address_b;
output [(width_a-1):0] q_a;
output [(width_b-1):0] q_b;
wire [(width_a-1):0] q_a_wire;
wire [(width_b-1):0] q_b_wire;
reg  clk_wire;


altsyncram altsyncram_component (
	.clock0 (clk_wire),
	.clock1 (1'd1),
	.clocken0 (clken),
	.clocken1 (1'd1),
	.clocken2 (1'd1),
	.clocken3 (1'd1),
	.aclr0 (1'd0),
	.aclr1 (1'd0),
	.addressstall_a (1'd0),
	.addressstall_b (1'd0),
	.eccstatus (),
	.address_a (address_a),
	.address_b (address_b),
	.rden_a (clken),
	.rden_b (clken),
	.q_a (q_a_wire),
	.q_b (q_b_wire),
	.byteena_a (),
	.byteena_b (),
	.wren_a (1'd0),
	.wren_b (1'd0),
	.data_a (),
	.data_b ()
);

defparam
	altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
	altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
	altsyncram_component.init_file = init_file,
	altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
	altsyncram_component.lpm_type = "altsyncram",
	altsyncram_component.power_up_uninitialized = "FALSE",
	altsyncram_component.intended_device_family = "Cyclone V",
	altsyncram_component.clock_enable_input_a = "BYPASS",
	altsyncram_component.clock_enable_input_b = "BYPASS",
	altsyncram_component.clock_enable_output_a = "BYPASS",
	altsyncram_component.clock_enable_output_b = "BYPASS",
	altsyncram_component.outdata_aclr_a = "NONE",
	altsyncram_component.outdata_aclr_b = "NONE",
	altsyncram_component.outdata_reg_a = "UNREGISTERED",
	altsyncram_component.outdata_reg_b = "UNREGISTERED",
	altsyncram_component.numwords_a = numwords_a,
	altsyncram_component.numwords_b = numwords_b,
	altsyncram_component.widthad_a = widthad_a,
	altsyncram_component.widthad_b = widthad_b,
	altsyncram_component.width_a = width_a,
	altsyncram_component.width_b = width_b,
	altsyncram_component.address_reg_b = "CLOCK0",
	altsyncram_component.byteena_reg_b = "CLOCK0",
	altsyncram_component.indata_reg_b = "CLOCK0",
	altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";


always @(*) begin
	clk_wire = clk;
end


integer j;
reg [(width_a-1):0] q_a_reg[latency:1], q_b_reg[latency:1];

always @(*)
begin
   q_a_reg[1] <= q_a_wire;
   q_b_reg[1] <= q_b_wire;
end

always @(posedge clk)
if (clken)
begin
   for (j = 1; j < latency; j=j+1)
   begin
       q_a_reg[j+1] <= q_a_reg[j];
       q_b_reg[j+1] <= q_b_reg[j];
   end
end

assign q_a = (clken) ? q_a_reg[latency] : 0;
assign q_b = (clken) ? q_b_reg[latency] : 0;

endmodule 
// Adding code from verilog file: ../../boards/Virtex6/ML605/top.v


module ML605 (
       USER_CLOCK,
	    KEY,
	    SW,	    
       LED,
       LEDG,
		UART_RXD,
		UART_TXD

	    );

   input USER_CLOCK;
   input [4:0] KEY;
   input [7:0] SW;
   output [7:0] LED;
   output [7:0] LEDG;
   wire CLOCK_50;

    input UART_RXD;
    output UART_TXD;    
	wire clk = CLOCK_50;
	wire go = ~KEY[1];



   wire 	reset = ~KEY[0];
   wire 	start;
   wire [31:0] 	return_val;
   reg  [31:0] 	return_val_reg;
   wire 	finish;
   wire [3:0]	state;
   
   reg [6:0]   hex0, hex1, hex2, hex3, hex4, hex5, hex6, hex7;

   assign CLOCK_50 = USER_CLOCK;
   assign LED = 0;
   
	always @ (*) begin
		hex7 <= return_val_reg[31:28];
		hex6 <= return_val_reg[27:24];
		hex5 <= return_val_reg[23:20];
		hex4 <= return_val_reg[19:16];
		hex3 <= return_val_reg[15:12];
		hex2 <= return_val_reg[11:8];
		hex1 <= return_val_reg[7:4];
		hex0 <= return_val_reg[3:0];
	end
assign UART_TXD = 1'b0;

    parameter s_WAIT = 3'b001, s_START = 3'b010, s_EXE = 3'b011,
                s_DONE = 3'b100;

    // state registers
    reg [3:0] y_Q, Y_D;

    assign LEDG[3:0] = y_Q;

    // next state
    always @(*)
    begin
        case (y_Q)
            s_WAIT: if (go) Y_D = s_START; else Y_D = y_Q;

            s_START: Y_D = s_EXE;

            s_EXE: if (!finish) Y_D = s_EXE; else Y_D = s_DONE;

            s_DONE: Y_D = s_DONE;

            default: Y_D = 3'bxxx;
        endcase
    end

    // current state
    always @(posedge clk)
    begin
        if (reset) // synchronous clear
            y_Q <= s_WAIT;
        else
            y_Q <= Y_D;
    end

    always @(posedge clk)
        if (y_Q == s_EXE && finish)
            return_val_reg <= return_val;
        else if (y_Q == s_DONE)
            return_val_reg <= return_val_reg;
        else
            return_val_reg <= 0;


    assign start = (y_Q == s_START);

   
   top top_inst (
      .clk (clk),
      .reset (reset),
      .finish (finish),
      .return_val (return_val),
        .start (start)

    );

   

endmodule

// Adding code from verilog file: ../../boards/StratixIV/DE4/top.v


module de4 ( 
    	     OSC_50_BANK2, 
             BUTTON, 
             LED, 
    	     SEG0_D, 
    	     SEG1_D 
	     ); 
   input OSC_50_BANK2; 
   input [1:0] BUTTON; 
   output [6:0] SEG0_D; 
   output [6:0] SEG1_D; 
   output [7:0] LED; 
   
   de2 de2_inst ( 
		  .CLOCK_50 (OSC_50_BANK2), 
		  .LEDG (LED), 
		  .KEY (BUTTON), 
		  .SW (), 
		  .HEX0 (SEG0_D), 
		  .HEX1 (SEG1_D), 
		  .HEX2 (), 
		  .HEX3 (), 
		  .HEX4 (), 
		  .HEX5 (), 
		  .HEX6 (), 
		  .HEX7 () 
		  ); 
   
endmodule
// Adding code from verilog file: ../../boards/CycloneII/DE2/top.v


module de2 (
	    CLOCK_50,
	    KEY,
	    SW,
	    HEX0,
	    HEX1,
	    HEX2,
	    HEX3,
	    HEX4,
	    HEX5,
	    HEX6,
	    HEX7,
	    LEDG,
		UART_RXD,
		UART_TXD

	    );

   input CLOCK_50;
   input [3:0] KEY;
   input [17:0] SW;
   output [6:0] HEX0, HEX1,  HEX2,  HEX3,  HEX4,  HEX5,  HEX6,  HEX7;
   reg [6:0] 	hex0, hex1, hex2, hex3, hex4, hex5, hex6, hex7;
   

   output [7:0] LEDG;
    input UART_RXD;
    output UART_TXD;    
	wire clk = CLOCK_50;
	wire go = ~KEY[1];



   wire 	reset = ~KEY[0];
   wire 	start;
   wire [31:0] 	return_val;
   reg  [31:0] 	return_val_reg;
   wire 	finish;
   wire [3:0]	state;

   hex_digits h7( .x(hex7), .hex_LEDs(HEX7));
   hex_digits h6( .x(hex6), .hex_LEDs(HEX6));
   hex_digits h5( .x(hex5), .hex_LEDs(HEX5));
   hex_digits h4( .x(hex4), .hex_LEDs(HEX4));
   hex_digits h3( .x(hex3), .hex_LEDs(HEX3));
   hex_digits h2( .x(hex2), .hex_LEDs(HEX2));
   hex_digits h1( .x(hex1), .hex_LEDs(HEX1));
   hex_digits h0( .x(hex0), .hex_LEDs(HEX0));
   
	always @ (*) begin
		hex7 <= return_val_reg[31:28];
		hex6 <= return_val_reg[27:24];
		hex5 <= return_val_reg[23:20];
		hex4 <= return_val_reg[19:16];
		hex3 <= return_val_reg[15:12];
		hex2 <= return_val_reg[11:8];
		hex1 <= return_val_reg[7:4];
		hex0 <= return_val_reg[3:0];
	end
assign UART_TXD = 1'b0;

    parameter s_WAIT = 3'b001, s_START = 3'b010, s_EXE = 3'b011,
                s_DONE = 3'b100;

    // state registers
    reg [3:0] y_Q, Y_D;

    assign LEDG[3:0] = y_Q;

    // next state
    always @(*)
    begin
        case (y_Q)
            s_WAIT: if (go) Y_D = s_START; else Y_D = y_Q;

            s_START: Y_D = s_EXE;

            s_EXE: if (!finish) Y_D = s_EXE; else Y_D = s_DONE;

            s_DONE: Y_D = s_DONE;

            default: Y_D = 3'bxxx;
        endcase
    end

    // current state
    always @(posedge clk)
    begin
        if (reset) // synchronous clear
            y_Q <= s_WAIT;
        else
            y_Q <= Y_D;
    end

    always @(posedge clk)
        if (y_Q == s_EXE && finish)
            return_val_reg <= return_val;
        else if (y_Q == s_DONE)
            return_val_reg <= return_val_reg;
        else
            return_val_reg <= 0;


    assign start = (y_Q == s_START);

   
   top top_inst (
      .clk (clk),
      .reset (reset),
      .finish (finish),
      .return_val (return_val),
        .start (start)

    );

endmodule

module circuit_start_control (
    go,
    control_key
);
    input control_key;
    output go;
    assign go = control_key;
endmodule
module hex_digits(x, hex_LEDs);
    input [3:0] x;
    output [6:0] hex_LEDs;
    
    assign hex_LEDs[0] = (~x[3] & ~x[2] & ~x[1] & x[0]) |
                            (~x[3] & x[2] & ~x[1] & ~x[0]) |
                            (x[3] & x[2] & ~x[1] & x[0]) |
                            (x[3] & ~x[2] & x[1] & x[0]);
    assign hex_LEDs[1] = (~x[3] & x[2] & ~x[1] & x[0]) |
                            (x[3] & x[1] & x[0]) |
                            (x[3] & x[2] & ~x[0]) |
                            (x[2] & x[1] & ~x[0]);
    assign hex_LEDs[2] = (x[3] & x[2] & ~x[0]) |
                            (x[3] & x[2] & x[1]) |
                            (~x[3] & ~x[2] & x[1] & ~x[0]);
    assign hex_LEDs[3] = (~x[3] & ~x[2] & ~x[1] & x[0]) | 
                            (~x[3] & x[2] & ~x[1] & ~x[0]) | 
                            (x[2] & x[1] & x[0]) | 
                            (x[3] & ~x[2] & x[1] & ~x[0]);
    assign hex_LEDs[4] = (~x[3] & x[0]) |
                            (~x[3] & x[2] & ~x[1]) |
                            (~x[2] & ~x[1] & x[0]);
    assign hex_LEDs[5] = (~x[3] & ~x[2] & x[0]) | 
                            (~x[3] & ~x[2] & x[1]) | 
                            (~x[3] & x[1] & x[0]) | 
                            (x[3] & x[2] & ~x[1] & x[0]);
    assign hex_LEDs[6] = (~x[3] & ~x[2] & ~x[1]) | 
                            (x[3] & x[2] & ~x[1] & ~x[0]) | 
                            (~x[3] & x[2] & x[1] & x[0]);
    
endmodule
`timescale 1 ns / 1 ns
module main_tb
(
);

reg  clk;
reg  reset;
reg  start;
reg  waitrequest;
wire [31:0] return_val;
wire  finish;


top top_inst (
	.clk (clk),
	.reset (reset),
	.start (start),
	.waitrequest (waitrequest),
	.finish (finish),
	.return_val (return_val)
);




initial 
    clk = 0;
always @(clk)
    clk <= #10 ~clk;

initial begin
//$monitor("At t=%t clk=%b %b %b %b %d", $time, clk, reset, start, finish, return_val);
@(negedge clk);
reset <= 1;
@(negedge clk);
reset <= 0;
start <= 1;
@(negedge clk);
start <= 0;
end

always@(finish) begin
    if (finish == 1) begin
        $display("At t=%t clk=%b finish=%b return_val=%d", $time, clk, finish, return_val);
        $display("Cycles: %d", ($time-50)/20);
        $finish;
    end
end

initial begin
waitrequest <= 1;
@(negedge clk);
@(negedge clk);
waitrequest <= 0;
end


endmodule