Skip to content

Commit 7df78b2

Browse files
timmy61109timmy61109
authored
Merge pull request #21 from timmy61109/feature/timmy61109/README.md
如果採用，此提交將修改說明文件
2 parents 5531bad + e590820 commit 7df78b2

File tree

1 file changed

+4
-1
lines changed

1 file changed

+4
-1
lines changed

‎README.md

+4-1
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,6 @@
11
Learn VHDL
22
===
3-
使用Altera Cyclone V SoC Kit學習使用FPGA與VHDL的過程檔案。
3+
使用Altera Cyclone V SoC Kit和Altera Cyclone III DE0學習使用FPGA與VHDL的過程檔案。
4+
使用的晶片:
5+
* Altera Cyclone V SoC Kit:5CSXFC6D6F31C8NES
6+
* Altera Cyclone III DE0:EP3C16F484C6N

0 commit comments

Comments
 (0)