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Update variable name to PYTHON3
1 parent f14a7fb commit 9880f6e

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-32
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4 files changed

+32
-32
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config.mk

+1-1
Original file line numberDiff line numberDiff line change
@@ -41,4 +41,4 @@ LDFLAGS = -O2 --memory-init-file 0 -s TOTAL_MEMORY=64*1024*1024
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SUBDIRS = icebox icepack icemulti icepll icetime icebram
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endif
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44-
PYTHON ?= python3
44+
PYTHON3 ?= python3

icebox/Makefile

+9-9
Original file line numberDiff line numberDiff line change
@@ -9,33 +9,33 @@ endif
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all: chipdb-384.txt chipdb-1k.txt chipdb-8k.txt chipdb-5k.txt chipdb-lm4k.txt chipdb-u4k.txt
1010

1111
chipdb-384.txt: icebox.py iceboxdb.py icebox_chipdb.py
12-
$(PYTHON) icebox_chipdb.py -3 > chipdb-384.new
12+
$(PYTHON3) icebox_chipdb.py -3 > chipdb-384.new
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mv chipdb-384.new chipdb-384.txt
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chipdb-1k.txt: icebox.py iceboxdb.py icebox_chipdb.py
16-
$(PYTHON) icebox_chipdb.py > chipdb-1k.new
16+
$(PYTHON3) icebox_chipdb.py > chipdb-1k.new
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mv chipdb-1k.new chipdb-1k.txt
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chipdb-5k.txt: icebox.py iceboxdb.py icebox_chipdb.py
20-
$(PYTHON) icebox_chipdb.py -5 > chipdb-5k.new
20+
$(PYTHON3) icebox_chipdb.py -5 > chipdb-5k.new
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mv chipdb-5k.new chipdb-5k.txt
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2323
chipdb-u4k.txt: icebox.py iceboxdb.py icebox_chipdb.py
24-
$(PYTHON) icebox_chipdb.py -u > chipdb-u4k.new
24+
$(PYTHON3) icebox_chipdb.py -u > chipdb-u4k.new
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mv chipdb-u4k.new chipdb-u4k.txt
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chipdb-lm4k.txt: icebox.py iceboxdb.py icebox_chipdb.py
28-
$(PYTHON) icebox_chipdb.py -4 > chipdb-lm4k.new
28+
$(PYTHON3) icebox_chipdb.py -4 > chipdb-lm4k.new
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mv chipdb-lm4k.new chipdb-lm4k.txt
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3131
chipdb-8k.txt: icebox.py iceboxdb.py icebox_chipdb.py
32-
$(PYTHON) icebox_chipdb.py -8 > chipdb-8k.new
32+
$(PYTHON3) icebox_chipdb.py -8 > chipdb-8k.new
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mv chipdb-8k.new chipdb-8k.txt
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check: all
36-
$(PYTHON) tc_xlat_netnames.py
37-
$(PYTHON) tc_rxlat_netnames.py
38-
$(PYTHON) tc_logic_xpr.py
36+
$(PYTHON3) tc_xlat_netnames.py
37+
$(PYTHON3) tc_rxlat_netnames.py
38+
$(PYTHON3) tc_logic_xpr.py
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clean:
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rm -f chipdb-1k.txt chipdb-8k.txt chipdb-384.txt chipdb-5k.txt chipdb-lm4k.txt chipdb-u4k.txt

icefuzz/Makefile

+20-20
Original file line numberDiff line numberDiff line change
@@ -76,8 +76,8 @@ ifneq ($(RAM_SUFFIX),_5k)
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cp cached_dsp3_5k.txt bitdata_dsp3_5k.txt
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cp cached_ipcon_5k.txt bitdata_ipcon_5k.txt
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endif
79-
ICEDEVICE=$(DEVICECLASS) $(PYTHON) database.py
80-
$(PYTHON) export.py
79+
ICEDEVICE=$(DEVICECLASS) $(PYTHON3) database.py
80+
$(PYTHON3) export.py
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diff -U0 cached_io.txt bitdata_io.txt || cp -v bitdata_io.txt cached_io.txt
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diff -U0 cached_logic.txt bitdata_logic.txt || cp -v bitdata_logic.txt cached_logic.txt
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diff -U0 cached_ramb$(RAM_SUFFIX).txt bitdata_ramb$(RAM_SUFFIX).txt || cp -v bitdata_ramb$(RAM_SUFFIX).txt cached_ramb$(RAM_SUFFIX).txt
@@ -91,53 +91,53 @@ endif
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timings:
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ifeq ($(DEVICECLASS),5k)
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cp tmedges.txt tmedges.tmp
94-
set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; sed '/defparam/d' < $$f > $$f.fixed; yosys -q -f verilog -s tmedges.ys $$f.fixed; $(PYTHON) rename_dsps.py $$f; done
94+
set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; sed '/defparam/d' < $$f > $$f.fixed; yosys -q -f verilog -s tmedges.ys $$f.fixed; $(PYTHON3) rename_dsps.py $$f; done
9595
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
96-
$(PYTHON) timings.py -t timings_up5k.txt work_*/*.sdf > timings_up5k.new
96+
$(PYTHON3) timings.py -t timings_up5k.txt work_*/*.sdf > timings_up5k.new
9797
mv timings_up5k.new timings_up5k.txt
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else
9999
ifeq ($(DEVICECLASS),u4k)
100100
cp tmedges.txt tmedges.tmp
101-
set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; sed '/defparam/d' < $$f > $$f.fixed; yosys -q -f verilog -s tmedges.ys $$f.fixed; $(PYTHON) rename_dsps.py $$f; done
101+
set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; sed '/defparam/d' < $$f > $$f.fixed; yosys -q -f verilog -s tmedges.ys $$f.fixed; $(PYTHON3) rename_dsps.py $$f; done
102102
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
103-
$(PYTHON) timings.py -t timings_u4k.txt work_*/*.sdf > timings_u4k.new
103+
$(PYTHON3) timings.py -t timings_u4k.txt work_*/*.sdf > timings_u4k.new
104104
mv timings_u4k.new timings_u4k.txt
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else
106106
ifeq ($(DEVICECLASS),8k)
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cp tmedges.txt tmedges.tmp
108108
set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
109109
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
110-
$(PYTHON) timings.py -t timings_hx8k.txt work_*/*.sdf > timings_hx8k.new
110+
$(PYTHON3) timings.py -t timings_hx8k.txt work_*/*.sdf > timings_hx8k.new
111111
mv timings_hx8k.new timings_hx8k.txt
112-
$(PYTHON) timings.py -t timings_lp8k.txt work_*/*.slp > timings_lp8k.new
112+
$(PYTHON3) timings.py -t timings_lp8k.txt work_*/*.slp > timings_lp8k.new
113113
mv timings_lp8k.new timings_lp8k.txt
114114
else
115115
ifeq ($(DEVICECLASS),384)
116116
cp tmedges.txt tmedges.tmp
117117
set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
118118
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
119-
$(PYTHON) timings.py -t timings_lp384.txt work_*/*.slp > timings_lp384.new
119+
$(PYTHON3) timings.py -t timings_lp384.txt work_*/*.slp > timings_lp384.new
120120
mv timings_lp384.new timings_lp384.txt
121121
else
122122
cp tmedges.txt tmedges.tmp
123123
set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
124124
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
125-
$(PYTHON) timings.py -t timings_hx1k.txt work_*/*.sdf > timings_hx1k.new
125+
$(PYTHON3) timings.py -t timings_hx1k.txt work_*/*.sdf > timings_hx1k.new
126126
mv timings_hx1k.new timings_hx1k.txt
127-
$(PYTHON) timings.py -t timings_lp1k.txt work_*/*.slp > timings_lp1k.new
127+
$(PYTHON3) timings.py -t timings_lp1k.txt work_*/*.slp > timings_lp1k.new
128128
mv timings_lp1k.new timings_lp1k.txt
129129
endif
130130
endif
131131
endif
132132
endif
133133
timings_html:
134-
$(PYTHON) timings.py -h tmedges.txt -t timings_hx1k.txt -l "HX1K with default temp/volt settings" > timings_hx1k.html
135-
$(PYTHON) timings.py -h tmedges.txt -t timings_hx8k.txt -l "HX8K with default temp/volt settings" > timings_hx8k.html
136-
$(PYTHON) timings.py -h tmedges.txt -t timings_lp1k.txt -l "LP1K with default temp/volt settings" > timings_lp1k.html
137-
$(PYTHON) timings.py -h tmedges.txt -t timings_lp8k.txt -l "LP8K with default temp/volt settings" > timings_lp8k.html
138-
$(PYTHON) timings.py -h tmedges.txt -t timings_lp384.txt -l "LP384 with default temp/volt settings" > timings_lp384.html
139-
$(PYTHON) timings.py -h tmedges.txt -t timings_up5k.txt -l "UP5K with default temp/volt settings" > timings_up5k.html
140-
$(PYTHON) timings.py -h tmedges.txt -t timings_u4k.txt -l "U4K with default temp/volt settings" > timings_u4k.html
134+
$(PYTHON3) timings.py -h tmedges.txt -t timings_hx1k.txt -l "HX1K with default temp/volt settings" > timings_hx1k.html
135+
$(PYTHON3) timings.py -h tmedges.txt -t timings_hx8k.txt -l "HX8K with default temp/volt settings" > timings_hx8k.html
136+
$(PYTHON3) timings.py -h tmedges.txt -t timings_lp1k.txt -l "LP1K with default temp/volt settings" > timings_lp1k.html
137+
$(PYTHON3) timings.py -h tmedges.txt -t timings_lp8k.txt -l "LP8K with default temp/volt settings" > timings_lp8k.html
138+
$(PYTHON3) timings.py -h tmedges.txt -t timings_lp384.txt -l "LP384 with default temp/volt settings" > timings_lp384.html
139+
$(PYTHON3) timings.py -h tmedges.txt -t timings_up5k.txt -l "UP5K with default temp/volt settings" > timings_up5k.html
140+
$(PYTHON3) timings.py -h tmedges.txt -t timings_u4k.txt -l "U4K with default temp/volt settings" > timings_u4k.html
141141
data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(RAM_SUFFIX).txt cached_ramt$(RAM_SUFFIX).txt cached_dsp0_5k.txt cached_dsp1_5k.txt cached_dsp2_5k.txt cached_dsp3_5k.txt cached_ipcon_5k.txt
142142
gawk '{ print "io", $$0; }' cached_io.txt > data_cached.new
143143
gawk '{ print "logic", $$0; }' cached_logic.txt >> data_cached.new
@@ -186,9 +186,9 @@ datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS)))
186186

187187
define data_template
188188
data_$(DEVICECLASS)_$(1).txt: make_$(1).py ../icepack/icepack
189-
ICEDEVICE=$(DEVICECLASS) $(PYTHON) make_$(1).py
189+
ICEDEVICE=$(DEVICECLASS) $(PYTHON3) make_$(1).py
190190
+ICEDEV=$(DEVICE) $(MAKE) -C work_$(DEVICECLASS)_$(1)
191-
ICEDEVICE=$(DEVICECLASS) $(PYTHON) extract.py work_$(DEVICECLASS)_$(1)/*.glb > $$@
191+
ICEDEVICE=$(DEVICECLASS) $(PYTHON3) extract.py work_$(DEVICECLASS)_$(1)/*.glb > $$@
192192
endef
193193

194194
$(foreach test,$(TESTS),$(eval $(call data_template,$(test))))

icetime/Makefile

+2-2
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ $(PROGRAM_PREFIX)icetime$(EXE): icetime.o iceutil.o $(addsuffix .o, $(addprefix
3232
$(CXX) -o $@ $(LDFLAGS) $^ $(LDLIBS)
3333

3434
timings-%.cc: timings.py ../icefuzz/timings_%.txt
35-
$(PYTHON) timings.py $* > $@
35+
$(PYTHON3) timings.py $* > $@
3636

3737
.PRECIOUS: timings-%.cc
3838

@@ -51,7 +51,7 @@ uninstall:
5151
# yosys -qp 'read_verilog -lib cells.v; prep; show' test0_out.v
5252

5353
test0 test1 test2 test3 test4 test5 test6 test7 test8 test9: icetime
54-
test -f $@_ref.v || python3 mktest.py $@
54+
test -f $@_ref.v || $(PYTHON3) mktest.py $@
5555
./icetime -m -d hx1k -P tq144 -p $@.pcf -o $@_out.v $@.asc
5656
yosys $@.ys
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