Edge-triggered SR flip flop, T flip flop

[JC3]

This is just a basic circuit but it took a minute to figure out so I figured I'd share it. Because this simulator is a logic simulator and not a physical circuit simulator, and thus doesn't simulate signal propagation delays, SR (and therefore T and D flip-flops) using traditional simple designs end up oscillating when the clock is high. In real life you can tune the clock pulse lengths so that they're just long enough to produce an output but just short enough to avoid seeing feedback (and so avoiding oscillations). In the simulator, you can't do that.

The solution is to use edge-triggered circuits instead of level triggered circuits. Here is a falling-edge-triggered SR flip flop based on the master/slave design here:

Here is a T flip flop based around that:

Here is an animation of them working:

https://www.youtube.com/watch?v=ucfTmZIVS2w

Hopefully this is useful to somebody!