VDD/VSS pins on macro not visible at top level

[Cronus-38]

Describe the bug

I'm running the hierarchical flow with a proprietary library. I create a macro by setting SYNTH_HIERARCHICAL=1 after specifying the block-level and top-level grid strategies using PDN script files.

The macro (aes_192) is built successfully, but during the top-level (aes_192_mock_tss) run the VDD and VSS pins (i.e. stripes) on the macro aren't present at the end of stage 2_4_floorplan_tapcell, despite the fact that the corresponding rectangles are present in the LEF file for the macro.

The missing VDD/VSS pins cause the following failure:

Running pdn.tcl, stage 2_5_floorplan_pdn
[INFO][FLOW] Using corner FuncRCmin
[INFO PDN-0001] Inserting grid: top
[INFO PDN-0001] Inserting grid: aes_192_Grid - aes_192_inst
[WARNING PDN-0232] aes_192_Grid - aes_192_inst does not contain any shapes or vias.
[ERROR PDN-0233] Failed to generate full power grid.
Error: pdn.tcl, 6 PDN-0233

Expected Behavior

I would like the top-level power grid to overlay the macro entirely. I don't want a power ring around the macro, rather I just want a grid in the macro and I want the top-level power grid to connect to the macro grid using vias where the stripes overlap. In other words, I'd like to see more or less the same result that's in the mock-array example, but it's not working. Could very well be a set up issue rather than a bug.

Environment

Here's my block-level PDN script:

add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$}
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$}
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDP$}
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDC$}
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VNW$}
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$}
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSC$}
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VPW$}

set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}

define_pdn_grid -name {block} -voltage_domains {CORE}
add_pdn_stripe -grid {block} -layer {M1} -width {0.096} -pitch {1.152} -offset {0} -followpins

add_pdn_stripe -grid {block} -layer {M3} -width {0.308} -spacing {0.332} -pitch {20} -offset {4.8}
add_pdn_stripe -grid {block} -layer {M4} -width {0.308} -spacing {0.332} -pitch {20} -offset {4.8}


add_pdn_connect -grid {block} -layers {M1 M3}
add_pdn_connect -grid {block} -layers {M3 M4}



Here's my top-level PDN script:

source $::env(SCRIPTS_DIR)/util.tcl

####################################
# global connections
####################################
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$}
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$}
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDP$}
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDC$}
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VNW$}
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$}
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSC$}
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VPW$}

####################################
# voltage domains
####################################
set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}

####################################
# standard cell grid
####################################
define_pdn_grid -name {top} -voltage_domains {CORE}
add_pdn_stripe -grid {top} -layer {M1} -width {0.096} -pitch {1.152} -offset {0} -followpins
add_pdn_ring   -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.140} -core_offset {0.504}

add_pdn_stripe -grid {top} -layer {M5} -width {0.308}  -spacing {0.332} -pitch {12.8} -offset {4.8} -extend_to_core_ring
add_pdn_stripe -grid {top} -layer {M6} -width {0.308} -spacing {0.140} -pitch {12.8} -offset {6.4} -extend_to_core_ring

add_pdn_connect -grid {top} -layers {M1 M5}
add_pdn_connect -grid {top} -layers {M1 M6}
add_pdn_connect -grid {top} -layers {M5 M6}

####################################
# Element grid
####################################
# The halo around the macro prevents pdn from blocking pin access

set macro_names {}

foreach macro [find_macros] {
  set macro_name [[$macro getMaster] getName]
  dict set macro_names $macro_name 1
}
set macro_names [dict keys $macro_names]

define_pdn_grid -macro -cells $macro_names \
    -halo "$::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y) $::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y)" \
    -voltage_domains {CORE} -name aes_192_Grid

add_pdn_connect -grid {aes_192_Grid} -layers {M5 M6}



In aes_192.lef I see the following:

MACRO aes_192
  FOREIGN aes_192 0 0 ;
  CLASS BLOCK ;
  SIZE 351.847 BY 351.847 ;
  PIN VDD
    USE POWER ;
    DIRECTION INOUT ;
    PORT
      LAYER M4 ;
        RECT  7.302 347.59 347.61 347.898 ;
        RECT  7.302 327.59 347.61 327.898 ;
        ...
        RECT  7.302 27.59 347.61 27.898 ;
        RECT  7.302 7.59 347.61 7.898 ;
      LAYER M3 ;
        RECT  347.302 2.832 347.61 349.68 ;
        RECT  327.302 2.832 327.61 349.68 ;
        RECT  307.302 2.832 307.61 349.68 ;
        ...

To Reproduce

I didn't include a script at this point because the library is proprietary, and I don't know yet if it's simply a setup issue.

Relevant log output

Screenshots

No response

Additional Context

No response