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cpu::intel: Make SSE4.1 conditional on SSSE3, clarify SSE3 comments.
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src/cpu/intel.rs

+6-13
Original file line numberDiff line numberDiff line change
@@ -236,8 +236,6 @@ fn cpuid_to_caps_and_set_c_flags(r: CpuidSummary) -> u32 {
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const _SSE_REQUIRED: () = assert!(cfg!(target_feature = "sse"));
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const _SSE2_REQUIRED: () = assert!(cfg!(target_feature = "sse2"));
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// TOOD: https://github.com/rust-lang/stdarch/issues/572
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#[cfg(all(target_arch = "x86", not(target_feature = "sse2")))]
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{
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// If somebody is trying to compile for an x86 target without SSE2
@@ -272,20 +270,15 @@ fn cpuid_to_caps_and_set_c_flags(r: CpuidSummary) -> u32 {
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// Intel: "12.7.2 Checking for SSSE3 Support"
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// If/when we support dynamic detection of SSE/SSE2, make this conditional
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// on SSE/SSE2.
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// TODO: Make this conditional on SSE3.
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if check(leaf1_ecx, 9) {
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set(&mut caps, Shift::Ssse3);
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}
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// Intel: "12.12.2 Checking for Intel SSE4.1 Support"
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// If/when we support dynamic detection of SSE/SSE2, make this conditional
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// on SSE/SSE2.
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// XXX: We don't check for SSE3 and we're not sure if it is compatible for
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// us to do so; does AMD advertise SSE3? TODO: address this.
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// XXX: We don't condition this on SSSE3 being available. TODO: address
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// this.
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#[cfg(target_arch = "x86_64")]
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if check(leaf1_ecx, 19) {
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set(&mut caps, Shift::Sse41);
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// Intel: "12.12.2 Checking for Intel SSE4.1 Support"
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#[cfg(target_arch = "x86_64")]
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if check(leaf1_ecx, 19) {
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set(&mut caps, Shift::Sse41);
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}
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}
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// AMD: "The extended SSE instructions include [...]."

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