Verible's formatter fails to lex/parse input

[joaovam]

Test case

module module_0 (  )  ; 
    assign  id_9  [  -1  -  -1  ]  =  0 ;  
endmodule

Command used: verible-verilog-format example.v --inplace

Actual output

example.v: Error lex/parsing-ing formatted output.  Please file a bug.
First error: token: "--" at 3:17-18:; problematic formatter output is
module module_0 ();
  assign id_9[-1--1] = 0;
endmodule

<<EOF>>

Version used

<unknown-git-version>
Commit  2025-02-06
Built   2025-02-20T11:40:59Z

[hzeller]

ah interesting case. Yes, there should be a space before that unary op.

I am currently busy with some other things, but if you'd like to send a PR to fix this, I am happy to look at it. Otherwise it might take a while.