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Copy pathsystem.mhs
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system.mhs
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PARAMETER VERSION = 2.1.0
PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
PORT processing_system7_0_PS_SRSTB = processing_system7_0_PS_SRSTB, DIR = IO
PORT processing_system7_0_PS_CLK = processing_system7_0_PS_CLK, DIR = IO, SIGIS = CLK
PORT processing_system7_0_PS_PORB = processing_system7_0_PS_PORB, DIR = IO
PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O
PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
PORT hdmi_clk = axi_hdmi_tx_16b_0_hdmi_clk, DIR = O
PORT hdmi_data = axi_hdmi_tx_16b_0_hdmi_data, DIR = O, VEC = [15:0]
PORT hdmi_hsync = axi_hdmi_tx_16b_0_hdmi_hsync, DIR = O
PORT hdmi_vsync = axi_hdmi_tx_16b_0_hdmi_vsync, DIR = O
PORT hdmi_data_e = axi_hdmi_tx_16b_0_hdmi_data_e, DIR = O
PORT hdmi_spdif = axi_spdif_tx_0_spdif_tx_o, DIR = O
PORT hdmi_int = hdmi_int, DIR = I, SIGIS = INTERRUPT
PORT otg_reset = net_vcc, DIR = O
PORT otg_vbusoc = net_otg_oc, DIR = I
PORT util_vector_logic_0_Op1_pin = net_util_vector_logic_0_Op1_pin, DIR = I, VEC = [0:0]
PORT axi_i2s_adi_0_BCLK_O_pin = axi_i2s_adi_0_BCLK_O, DIR = O, SIGIS = CLK
PORT axi_i2s_adi_0_LRCLK_O_pin = axi_i2s_adi_0_LRCLK_O, DIR = O, SIGIS = CLK
PORT axi_i2s_adi_0_SDATA_I_pin = axi_i2s_adi_0_SDATA_I, DIR = I
PORT axi_i2s_adi_0_SDATA_O_pin = axi_i2s_adi_0_SDATA_O, DIR = O
PORT axi_i2s_adi_0_MCLK_pin = clock_generator_0_CLKOUT0, DIR = O
PORT util_i2c_mixer_0_downstream_scl_pin = util_i2c_mixer_0_downstream_scl, DIR = IO, VEC = [1:0]
PORT util_i2c_mixer_0_downstream_sda_pin = util_i2c_mixer_0_downstream_sda, DIR = IO, VEC = [1:0]
PORT processing_system7_0_GPIO_pin = processing_system7_0_GPIO, DIR = IO, VEC = [10:0]
BEGIN processing_system7
PARAMETER INSTANCE = processing_system7_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_DDR_RAM_HIGHADDR = 0x1FFFFFFF
PARAMETER C_EN_EMIO_CAN0 = 0
PARAMETER C_EN_EMIO_CAN1 = 0
PARAMETER C_EN_EMIO_ENET0 = 0
PARAMETER C_EN_EMIO_ENET1 = 0
PARAMETER C_EN_EMIO_I2C0 = 1
PARAMETER C_EN_EMIO_I2C1 = 0
PARAMETER C_EN_EMIO_PJTAG = 0
PARAMETER C_EN_EMIO_SDIO0 = 0
PARAMETER C_EN_EMIO_SDIO1 = 0
PARAMETER C_EN_EMIO_SPI0 = 0
PARAMETER C_EN_EMIO_SPI1 = 0
PARAMETER C_EN_EMIO_SRAM_INT = 0
PARAMETER C_EN_EMIO_TRACE = 0
PARAMETER C_EN_EMIO_TTC0 = 1
PARAMETER C_EN_EMIO_TTC1 = 0
PARAMETER C_EN_EMIO_UART0 = 0
PARAMETER C_EN_EMIO_UART1 = 0
PARAMETER C_EN_EMIO_MODEM_UART0 = 0
PARAMETER C_EN_EMIO_MODEM_UART1 = 0
PARAMETER C_EN_EMIO_USB0 = 0
PARAMETER C_EN_EMIO_USB1 = 0
PARAMETER C_EN_EMIO_WDT = 0
PARAMETER C_EN_QSPI = 1
PARAMETER C_EN_SMC = 0
PARAMETER C_EN_CAN0 = 0
PARAMETER C_EN_CAN1 = 0
PARAMETER C_EN_ENET0 = 1
PARAMETER C_EN_ENET1 = 0
PARAMETER C_EN_I2C0 = 1
PARAMETER C_EN_I2C1 = 0
PARAMETER C_EN_PJTAG = 0
PARAMETER C_EN_SDIO0 = 1
PARAMETER C_EN_SDIO1 = 0
PARAMETER C_EN_SPI0 = 0
PARAMETER C_EN_SPI1 = 0
PARAMETER C_EN_TRACE = 0
PARAMETER C_EN_TTC0 = 1
PARAMETER C_EN_TTC1 = 0
PARAMETER C_EN_UART0 = 0
PARAMETER C_EN_UART1 = 1
PARAMETER C_EN_MODEM_UART0 = 0
PARAMETER C_EN_MODEM_UART1 = 0
PARAMETER C_EN_USB0 = 1
PARAMETER C_EN_USB1 = 0
PARAMETER C_EN_WDT = 0
PARAMETER C_EN_DDR = 1
PARAMETER C_FCLK_CLK0_FREQ = 100000000
PARAMETER C_FCLK_CLK1_FREQ = 200000000
PARAMETER C_FCLK_CLK2_FREQ = 200000000
PARAMETER C_FCLK_CLK3_FREQ = 76923080
PARAMETER C_USE_M_AXI_GP0 = 1
PARAMETER C_USE_S_AXI_HP0 = 1
PARAMETER C_USE_S_AXI_HP2 = 1
PARAMETER C_INTERCONNECT_S_AXI_HP0_MASTERS = axi_vdma_0.M_AXI_MM2S
PARAMETER C_INTERCONNECT_S_AXI_HP2_MASTERS = axi_dma_spdif.M_AXI_MM2S & axi_dma_spdif.M_AXI_SG & axi_dma_i2s.M_AXI_MM2S & axi_dma_i2s.M_AXI_SG & axi_dma_i2s.M_AXI_S2MM
PARAMETER C_EN_GPIO = 1
PARAMETER C_EMIO_GPIO_WIDTH = 11
PARAMETER C_EN_EMIO_GPIO = 1
BUS_INTERFACE M_AXI_GP0 = axi_interconnect_1
BUS_INTERFACE S_AXI_HP0 = axi_interconnect_2
BUS_INTERFACE S_AXI_HP2 = axi_interconnect_0
PORT MIO = processing_system7_0_MIO
PORT PS_SRSTB = processing_system7_0_PS_SRSTB
PORT PS_CLK = processing_system7_0_PS_CLK
PORT PS_PORB = processing_system7_0_PS_PORB
PORT DDR_Clk = processing_system7_0_DDR_Clk
PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
PORT DDR_CKE = processing_system7_0_DDR_CKE
PORT DDR_CS_n = processing_system7_0_DDR_CS_n
PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
PORT DDR_WEB = processing_system7_0_DDR_WEB
PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
PORT DDR_Addr = processing_system7_0_DDR_Addr
PORT DDR_ODT = processing_system7_0_DDR_ODT
PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
PORT DDR_DQ = processing_system7_0_DDR_DQ
PORT DDR_DM = processing_system7_0_DDR_DM
PORT DDR_DQS = processing_system7_0_DDR_DQS
PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
PORT DDR_VRN = processing_system7_0_DDR_VRN
PORT DDR_VRP = processing_system7_0_DDR_VRP
PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0
PORT FCLK_CLK1 = processing_system7_0_FCLK_CLK1
PORT FCLK_CLK2 = processing_system7_0_FCLK_CLK2
PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N
PORT FCLK_RESET1_N = processing_system7_0_FCLK_RESET1_N
PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK0
PORT S_AXI_HP0_ACLK = processing_system7_0_FCLK_CLK1
PORT S_AXI_HP2_ACLK = processing_system7_0_FCLK_CLK0
PORT IRQ_F2P = axi_vdma_0_mm2s_introut & axi_dma_spdif_mm2s_introut & hdmi_int & axi_dma_i2s_s2mm_introut & axi_dma_i2s_mm2s_introut
PORT USB0_VBUS_PWRFAULT = util_vector_logic_0_Res
PORT GPIO = processing_system7_0_GPIO
PORT I2C0_SCL_T = processing_system7_0_I2C0_SCL_T
PORT I2C0_SDA_T = processing_system7_0_I2C0_SDA_T
PORT I2C0_SCL_O = processing_system7_0_I2C0_SCL_O
PORT I2C0_SDA_O = processing_system7_0_I2C0_SDA_O
PORT I2C0_SCL_I = util_i2c_mixer_0_upstream_scl_O
PORT I2C0_SDA_I = util_i2c_mixer_0_upstream_sda_O
END
BEGIN axi_vdma
PARAMETER INSTANCE = axi_vdma_0
PARAMETER HW_VER = 5.04.a
PARAMETER C_USE_FSYNC = 1
PARAMETER C_INCLUDE_S2MM = 0
PARAMETER C_M_AXI_MM2S_DATA_WIDTH = 64
PARAMETER C_M_AXIS_MM2S_TDATA_WIDTH = 64
PARAMETER C_MM2S_LINEBUFFER_THRESH = 8
PARAMETER C_BASEADDR = 0x43000000
PARAMETER C_HIGHADDR = 0x4300ffff
BUS_INTERFACE S_AXI_LITE = axi_interconnect_1
BUS_INTERFACE M_AXI_MM2S = axi_interconnect_2
BUS_INTERFACE M_AXIS_MM2S = axi_vdma_0_M_AXIS_MM2S
PORT m_axis_mm2s_aclk = processing_system7_0_FCLK_CLK1
PORT mm2s_fsync_out = axi_vdma_0_mm2s_fsync_out
PORT mm2s_buffer_almost_empty = axi_vdma_0_mm2s_buffer_almost_empty
PORT mm2s_buffer_empty = axi_vdma_0_mm2s_buffer_empty
PORT mm2s_fsync = axi_hdmi_tx_16b_0_vdma_fs
PORT s_axi_lite_aclk = processing_system7_0_FCLK_CLK0
PORT m_axi_mm2s_aclk = processing_system7_0_FCLK_CLK1
PORT mm2s_introut = axi_vdma_0_mm2s_introut
END
BEGIN axi_interconnect
PARAMETER INSTANCE = axi_interconnect_1
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
END
BEGIN axi_interconnect
PARAMETER INSTANCE = axi_interconnect_2
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 1
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK1
PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET1_N
END
BEGIN axi_hdmi_tx_16b
PARAMETER INSTANCE = axi_hdmi_tx_16b_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x6c000000
PARAMETER C_HIGHADDR = 0x6c00ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
BUS_INTERFACE M_AXIS_MM2S = axi_vdma_0_M_AXIS_MM2S
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT hdmi_ref_clk = axi_hdmi_tx_16b_0_hdmi_ref_clk
PORT hdmi_clk = axi_hdmi_tx_16b_0_hdmi_clk
PORT hdmi_data = axi_hdmi_tx_16b_0_hdmi_data
PORT hdmi_hsync = axi_hdmi_tx_16b_0_hdmi_hsync
PORT hdmi_vsync = axi_hdmi_tx_16b_0_hdmi_vsync
PORT hdmi_data_e = axi_hdmi_tx_16b_0_hdmi_data_e
PORT vdma_clk = processing_system7_0_FCLK_CLK1
PORT vdma_fs = axi_hdmi_tx_16b_0_vdma_fs
PORT vdma_fs_ret = axi_vdma_0_mm2s_fsync_out
PORT vdma_empty = axi_vdma_0_mm2s_buffer_empty
PORT vdma_almost_empty = axi_vdma_0_mm2s_buffer_almost_empty
END
BEGIN axi_dma
PARAMETER INSTANCE = axi_dma_spdif
PARAMETER HW_VER = 5.00.a
PARAMETER C_INCLUDE_S2MM = 0
PARAMETER C_INCLUDE_SG = 1
PARAMETER C_SG_INCLUDE_STSCNTRL_STRM = 0
PARAMETER C_BASEADDR = 0x40400000
PARAMETER C_HIGHADDR = 0x4040ffff
PARAMETER C_SG_LENGTH_WIDTH = 20
BUS_INTERFACE S_AXI_LITE = axi_interconnect_1
BUS_INTERFACE M_AXI_MM2S = axi_interconnect_0
BUS_INTERFACE M_AXIS_MM2S = axi_dma_spdif_M_AXIS_MM2S
BUS_INTERFACE M_AXI_SG = axi_interconnect_0
PORT s_axi_lite_aclk = processing_system7_0_FCLK_CLK0
PORT m_axi_mm2s_aclk = processing_system7_0_FCLK_CLK0
PORT mm2s_introut = axi_dma_spdif_mm2s_introut
PORT m_axi_sg_aclk = processing_system7_0_FCLK_CLK0
END
BEGIN axi_spdif_tx
PARAMETER INSTANCE = axi_spdif_tx_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x75c00000
PARAMETER C_HIGHADDR = 0x75c0ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
BUS_INTERFACE S_AXIS_MM2S = axi_dma_spdif_M_AXIS_MM2S
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT ACLK = processing_system7_0_FCLK_CLK0
PORT spdif_tx_o = axi_spdif_tx_0_spdif_tx_o
PORT spdif_data_clk = clock_generator_0_CLKOUT0
PORT spdif_tx_int_o = axi_spdif_tx_0_spdif_tx_int_o
END
BEGIN axi_interconnect
PARAMETER INSTANCE = axi_interconnect_0
PARAMETER HW_VER = 1.06.a
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END
BEGIN axi_clkgen
PARAMETER INSTANCE = axi_clkgen_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x66000000
PARAMETER C_HIGHADDR = 0x6600ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT ref_clk = processing_system7_0_FCLK_CLK2
PORT clk = axi_hdmi_tx_16b_0_hdmi_ref_clk
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 4.03.a
PARAMETER C_CLKIN_FREQ = 200000000
PARAMETER C_CLKOUT0_FREQ = 12288135
PORT RST = net_gnd
PORT CLKOUT0 = clock_generator_0_CLKOUT0
PORT CLKIN = processing_system7_0_FCLK_CLK2
END
BEGIN util_vector_logic
PARAMETER INSTANCE = util_vector_logic_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_OPERATION = not
PARAMETER C_SIZE = 1
PORT Res = util_vector_logic_0_Res
PORT Op1 = net_otg_oc
END
BEGIN axi_i2s_adi
PARAMETER INSTANCE = axi_i2s_adi_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x77600000
PARAMETER C_HIGHADDR = 0x7760FFFF
PARAMETER C_BCLK_POL = 0
PARAMETER C_LRCLK_POL = 0
PARAMETER C_FRM_SYNC = 0
BUS_INTERFACE S_AXI = axi_interconnect_1
BUS_INTERFACE S_AXIS_MM2S = axi_dma_i2s_M_AXIS_MM2S
BUS_INTERFACE M_AXIS_S2MM = axi_i2s_adi_0_M_AXIS_S2MM
PORT DATA_CLK_I = clock_generator_0_CLKOUT0
PORT BCLK_O = axi_i2s_adi_0_BCLK_O
PORT LRCLK_O = axi_i2s_adi_0_LRCLK_O
PORT SDATA_I = axi_i2s_adi_0_SDATA_I
PORT SDATA_O = axi_i2s_adi_0_SDATA_O
PORT ACLK = processing_system7_0_FCLK_CLK0
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT M_AXIS_ACLK = processing_system7_0_FCLK_CLK0
END
BEGIN util_i2c_mixer
PARAMETER INSTANCE = util_i2c_mixer_0
PARAMETER HW_VER = 1.00.a
PORT downstream_scl = util_i2c_mixer_0_downstream_scl
PORT downstream_sda = util_i2c_mixer_0_downstream_sda
PORT upstream_scl_T = processing_system7_0_I2C0_SCL_T
PORT upstream_sda_T = processing_system7_0_I2C0_SDA_T
PORT upstream_scl_I = processing_system7_0_I2C0_SCL_O
PORT upstream_sda_I = processing_system7_0_I2C0_SDA_O
PORT upstream_scl_O = util_i2c_mixer_0_upstream_scl_O
PORT upstream_sda_O = util_i2c_mixer_0_upstream_sda_O
END
BEGIN axi_dma
PARAMETER INSTANCE = axi_dma_i2s
PARAMETER HW_VER = 5.00.a
PARAMETER C_INCLUDE_S2MM = 1
PARAMETER C_INCLUDE_SG = 1
PARAMETER C_SG_INCLUDE_STSCNTRL_STRM = 0
PARAMETER C_BASEADDR = 0x40410000
PARAMETER C_HIGHADDR = 0x4041ffff
PARAMETER C_SG_LENGTH_WIDTH = 20
PARAMETER C_SG_USE_STSAPP_LENGTH = 0
BUS_INTERFACE S_AXI_LITE = axi_interconnect_1
BUS_INTERFACE M_AXI_MM2S = axi_interconnect_0
BUS_INTERFACE M_AXI_SG = axi_interconnect_0
BUS_INTERFACE M_AXIS_MM2S = axi_dma_i2s_M_AXIS_MM2S
BUS_INTERFACE M_AXI_S2MM = axi_interconnect_0
BUS_INTERFACE S_AXIS_S2MM = axi_i2s_adi_0_M_AXIS_S2MM
PORT s_axi_lite_aclk = processing_system7_0_FCLK_CLK0
PORT m_axi_mm2s_aclk = processing_system7_0_FCLK_CLK0
PORT mm2s_introut = axi_dma_i2s_mm2s_introut
PORT s2mm_introut = axi_dma_i2s_s2mm_introut
PORT m_axi_sg_aclk = processing_system7_0_FCLK_CLK0
PORT m_axi_s2mm_aclk = processing_system7_0_FCLK_CLK0
END