From 8e239763f834c9a3e1e36a71a931fd6cce6b3fe6 Mon Sep 17 00:00:00 2001
From: Devyn Cairns <devyn.cairns@gmail.com>
Date: Sat, 12 Aug 2023 17:44:35 -0700
Subject: [PATCH] add asm for other riscv instruction formats

---
 stage2/11-riscv-optimized.lsp | 70 +++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/stage2/11-riscv-optimized.lsp b/stage2/11-riscv-optimized.lsp
index 962adcc..cd9042b 100644
--- a/stage2/11-riscv-optimized.lsp
+++ b/stage2/11-riscv-optimized.lsp
@@ -94,3 +94,73 @@
   ))
 (define rv.format.u (quote
   (car (call-native rv.format.u$ 1 opcode rd imm))))
+
+(define rv.format.b$
+  (poke.w (allocate (<< 27 2) 4)
+    (\andi $a0 $a0 rv.opcode-mask)
+    (\andi $a1 $a1 rv.funct3-mask)
+    (\andi $a2 $a2 rv.reg-mask)
+    (\andi $a3 $a3 rv.reg-mask)
+    (\slli $a1 $a1 12) ; funct3
+    (\slli $a2 $a2 15) ; rs1
+    (\slli $a3 $a3 20) ; rs2
+    ; split imm into four pieces
+    ; (<< (& (>> imm 11) 1) 7)
+    (\srli $t0 $a4 11)
+    (\andi $t0 $t0 1)
+    (\slli $t0 $t0 7)
+    ; (<< (& (>> imm 1) (bit-mask 4)) 8)
+    (\srli $t1 $a4 1)
+    (\andi $t1 $t1 (bit-mask 4))
+    (\slli $t1 $t1 8)
+    ; (<< (& (>> imm 5) (bit-mask 6)) 25)
+    (\srli $t2 $a4 5)
+    (\andi $t2 $t2 (bit-mask 6))
+    (\slli $t2 $t2 25)
+    ; (<< (& (>> imm 12) 1) 31)
+    (\srli $t3 $a4 12)
+    (\andi $t3 $t3 1)
+    (\slli $t3 $t3 31)
+    (\or   $a0 $a0 $a1)
+    (\or   $a0 $a0 $a2)
+    (\or   $a0 $a0 $a3)
+    (\or   $a0 $a0 $t0)
+    (\or   $a0 $a0 $t1)
+    (\or   $a0 $a0 $t2)
+    (\or   $a0 $a0 $t3)
+    (\ret)
+  ))
+(define rv.format.b (quote
+  (car (call-native rv.format.b$ 1 opcode funct3 rs1 rs2 imm))))
+
+(define rv.format.j$
+  (poke.w (allocate (<< 21 2) 4)
+    (\andi $a0 $a0 rv.opcode-mask)
+    (\andi $a1 $a1 rv.reg-mask)
+    (\slli $a1 $a1 7) ; rd
+    ; split imm into 4 fields
+    ; (& imm (<< (bit-mask 8) 12))
+    (\li   $t0 (bit-mask 8))
+    (\slli $t0 $t0 12)
+    (\and  $t0 $a2 $t0)
+    ; (<< (& (>> imm 11) 1) 20)
+    (\srli $t1 $a2 11)
+    (\andi $t1 $t1 1)
+    (\slli $t1 $t1 20)
+    ; (<< (& (>> imm 1) (bit-mask 10)) 21)
+    (\srli $t2 $a2 1)
+    (\andi $t2 $t2 (bit-mask 10))
+    (\slli $t2 $t2 21)
+    ; (<< (& (>> imm 20) 1) 31)
+    (\srli $t3 $a2 20)
+    (\andi $t3 $t3 1)
+    (\slli $t3 $t3 31)
+    (\or   $a0 $a0 $a1)
+    (\or   $a0 $a0 $t0)
+    (\or   $a0 $a0 $t1)
+    (\or   $a0 $a0 $t2)
+    (\or   $a0 $a0 $t3)
+    (\ret)
+  ))
+(define rv.format.j (quote
+  (car (call-native rv.format.j$ 1 opcode rd imm))))