Yosys support?

[dvdrndlph]

I am having problems using Yosys in your workflow. I linked in the circuit_synthesis/lib/asic_cell_yosys_extended.lib file and removed all of the /^\s*(*/ comment lines in the synthesized (netlist) output. (These steps should be documented.) This allowed me to generate SCD for the following trivial Verilog circuit:

module andy(g_input, e_input, o);
    input[0:0] g_input;
    input[0:0] e_input;
    output[0:0] o;
    assign o[0] = g_input[0] & e_input[0];
endmodule

But I am failing (at the SCD generation step) with Verilog like this:

module nibbler(clk, g_input, e_input, o);
  parameter input_len = 128, record_len = 8, output_len = 32;
  input wire clk;
  input wire[0:input_len-1] g_input, e_input;
  output wire [0:output_len-1] o;

  reg enabled = 1'b0;
  integer g_i = 0, e_i = 0;
  reg[0:record_len-1] g, e;
  reg[0:output_len-1] o_reg = 0;
  assign o = o_reg;

  always @(posedge clk) begin
    if (e_i == input_len) begin
      g_i = g_i + record_len;
      e_i = 0;
    end
    if (enabled) begin
      if ((e[0:3] == g[0:3] | e[4:7] == g[4:7])) begin
        o_reg = o_reg + 1;
      end
      enabled = 1'b0;
    end else begin
      g = g_input[g_i+:record_len];
      e = e_input[e_i+:record_len];
      e_i = e_i + record_len;
      enabled = 1'b1;
    end
  end
endmodule

V2SCD_Main dumps core without generating anything in the error log. The info.log just says this:

v_2_scd_main.cpp:79 ^[[32mINFO^[[0m: V2SCD /tmp/nibbler_syn.v to /tmp/nibbler.scd

Any pointers you could provide to help me get this working would be appreciated.