diff --git a/src/PMURegisterDeclarations/GenuineIntel-6-AE-0.json b/src/PMURegisterDeclarations/GenuineIntel-6-AE-0.json new file mode 100644 index 00000000..d68375b7 --- /dev/null +++ b/src/PMURegisterDeclarations/GenuineIntel-6-AE-0.json @@ -0,0 +1,158 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, + "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed3" : { + "OS": {"Config": 0, "Position": 12, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 13, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 15, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "PerfMetrics": {"Config": 2, "Position": 0, "Width": 1, "DefaultValue": 0, "__comment": "fake field to tell the collector to also print the L1 top-down metrics, not just raw slots count"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, + "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "xpi" : { + "__comment" : "this is for UPI LL and QPI LL uncore PMUs", + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} + } + }, + "m2m" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} + } + }, + "m3upi" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "mdf" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex8" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex16" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "iio" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, + "PortMask": {"Config": 0, "Position": 36, "Width": 12}, + "FCMask": {"Config": 0, "Position": 48, "Width": 3} + } + } +} diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index e21f3909..d0bbabdc 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -751,6 +751,7 @@ void PCM::initCStateSupportTables() case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: PCM_CSTATE_ARRAY(pkgCStateMsr, PCM_PARAM_PROTECT({0, 0, 0x60D, 0, 0, 0, 0x3F9, 0, 0, 0, 0}) ); @@ -810,6 +811,7 @@ void PCM::initCStateSupportTables() case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: PCM_CSTATE_ARRAY(coreCStateMsr, PCM_PARAM_PROTECT({0, 0, 0, 0x3FC, 0, 0, 0x3FD, 0x3FE, 0, 0, 0}) ); @@ -1689,6 +1691,7 @@ bool PCM::detectNominalFrequency() || cpu_family_model == SPR || cpu_family_model == EMR || cpu_family_model == GNR + || cpu_family_model == GNR_D || cpu_family_model == SRF || cpu_family_model == GRR ) ? (100000000ULL) : (133333333ULL); @@ -1995,6 +1998,7 @@ void PCM::initUncoreObjects() case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: { @@ -2182,6 +2186,7 @@ void PCM::initUncorePMUsDirect() break; case SRF: case GNR: + case GNR_D: uncorePMUs[s].resize(1); { std::vector > CounterControlRegs{ @@ -2330,6 +2335,7 @@ void PCM::initUncorePMUsDirect() case SPR: case EMR: case GNR: + case GNR_D: case SRF: uncorePMUs[s].resize(1); addPMUsFromDiscoveryRef(uncorePMUs[s][0][PCU_PMU_ID], SPR_PCU_BOX_TYPE, 0xE); @@ -2357,6 +2363,7 @@ void PCM::initUncorePMUsDirect() addMDFPMUs(SPR_MDF_BOX_TYPE); break; case GNR: + case GNR_D: case SRF: addMDFPMUs(BHS_MDF_BOX_TYPE); break; @@ -2404,6 +2411,7 @@ void PCM::initUncorePMUsDirect() switch (cpu_family_model) { case GNR: + case GNR_D: case GRR: case SRF: uncorePMUs[s].resize(1); @@ -2510,6 +2518,7 @@ void PCM::initUncorePMUsDirect() } break; case PCM::GNR: + case PCM::GNR_D: case PCM::SRF: for (uint32 s = 0; s < (uint32)num_sockets; ++s) { @@ -2630,7 +2639,7 @@ void PCM::initUncorePMUsDirect() { static const uint32 IAA_DEV_IDS[] = { 0x0CFE }; static const uint32 DSA_DEV_IDS[] = { 0x0B25 }; - static const uint32 QAT_DEV_IDS[] = { 0x4940, 0x4942, 0x4944 }; + static const uint32 QAT_DEV_IDS[] = { 0x4940, 0x4942, 0x4944, 0x4946, 0x578a }; std::vector > socket2IAAbus; std::vector > socket2DSAbus; std::vector > socket2QATbus; @@ -2692,7 +2701,7 @@ void PCM::initUncorePMUsDirect() std::hex << std::setw(4) << std::setfill('0') << devInfo.domain << ":" << std::hex << std::setw(2) << std::setfill('0') << devInfo.bus << ":" << std::hex << std::setw(2) << std::setfill('0') << devInfo.dev << "." << - std::hex << devInfo.func << "/telemetry/control"; + std::hex << devInfo.func << "/telemetry/control"; qatTLMCTLStr = readSysFS(qat_TLMCTL_sysfs_path.str().c_str(), true); if(!qatTLMCTLStr.size()){ std::cerr << "Warning: IDX - QAT telemetry feature of B:0x" << std::hex << devInfo.bus << ",D:0x" << devInfo.dev << ",F:0x" << devInfo.func \ @@ -2740,6 +2749,7 @@ void PCM::initUncorePMUsDirect() IRP_UNIT_CTL = SPR_IRP_UNIT_CTL; break; case GNR: + case GNR_D: case SRF: irpStacks = BHS_M2IOSF_NUM; IRP_CTL_REG_OFFSET = BHS_IRP_CTL_REG_OFFSET; @@ -2881,6 +2891,7 @@ void PCM::initUncorePMUsDirect() case PCM::SPR: case PCM::EMR: case PCM::GNR: + case PCM::GNR_D: case PCM::SRF: { const auto n_units = (std::min)(uncorePMUDiscovery->getNumBoxes(SPR_CXLCM_BOX_TYPE, s), @@ -3372,6 +3383,7 @@ bool PCM::isCPUModelSupported(const int model_) || model_ == SPR || model_ == EMR || model_ == GNR + || model_ == GNR_D || model_ == GRR || model_ == SRF ); @@ -3417,9 +3429,6 @@ bool PCM::checkModel() case RPL_3: cpu_family_model = RPL; break; - case GNR_D: - cpu_family_model = GNR; - break; } if(!isCPUModelSupported((int)cpu_family_model)) @@ -3698,6 +3707,7 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter case SPR: case EMR: case GNR: + case GNR_D: assert(useSkylakeEvents()); coreEventDesc[0].event_number = SKL_MEM_LOAD_RETIRED_L3_MISS_EVTNR; coreEventDesc[0].umask_value = SKL_MEM_LOAD_RETIRED_L3_MISS_UMASK; @@ -5023,6 +5033,8 @@ const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const return "Emerald Rapids-SP"; case GNR: return "Granite Rapids-SP"; + case GNR_D: + return "Granite Rapids-D"; case GRR: return "Grand Ridge"; case SRF: @@ -7813,6 +7825,19 @@ void ServerUncorePMUs::initRegisterLocations(const PCM * pcm) PCM_PCICFG_M3UPI_INIT(5, BHS); } break; + case PCM::GNR_D: + { + // B2CMI (M2M) + PCM_PCICFG_M2M_INIT(0, BHS) + PCM_PCICFG_M2M_INIT(1, BHS) + PCM_PCICFG_M2M_INIT(2, BHS) + PCM_PCICFG_M2M_INIT(3, BHS) + PCM_PCICFG_M2M_INIT(4, BHS) + PCM_PCICFG_M2M_INIT(5, BHS) + PCM_PCICFG_M2M_INIT(6, BHS) + PCM_PCICFG_M2M_INIT(7, BHS) + } + break; case PCM::SNOWRIDGE: { PCM_PCICFG_M2M_INIT(0, SERVER) @@ -8015,6 +8040,7 @@ void ServerUncorePMUs::initDirect(uint32 socket_, const PCM * pcm) case PCM::SPR: case PCM::EMR: case PCM::GNR: // B2CMI PMUs + case PCM::GNR_D: case PCM::SRF: m2mPMUs.push_back( UncorePMU( @@ -8183,7 +8209,7 @@ void ServerUncorePMUs::initDirect(uint32 socket_, const PCM * pcm) } } - auto initBHSiMCPMUs = [&](const size_t numChannelsParam) + auto initBHSiMCPMUsBase = [&](const size_t base, const size_t numChannelsParam) { numChannels = (std::min)(numChannelsParam, m2mPMUs.size()); if (initAndCheckSocket2Ubox0Bus()) @@ -8191,12 +8217,17 @@ void ServerUncorePMUs::initDirect(uint32 socket_, const PCM * pcm) auto memBar = getServerSCFBar(socket2UBOX0bus[socket_].first, socket2UBOX0bus[socket_].second); for (int channel = 0; channel < numChannels; ++channel) { - imcPMUs.push_back(createIMCPMU(memBar + BHS_MC_CH_PMON_BASE_ADDR + channel * SERVER_MC_CH_PMON_STEP, SERVER_MC_CH_PMON_SIZE)); + imcPMUs.push_back(createIMCPMU(memBar + base + channel * SERVER_MC_CH_PMON_STEP, SERVER_MC_CH_PMON_SIZE)); num_imc_channels.push_back(1); } } }; + auto initBHSiMCPMUs = [&](const size_t numChannelsParam) + { + initBHSiMCPMUsBase(BHS_MC_CH_PMON_BASE_ADDR, numChannelsParam); + }; + switch (cpu_family_model) { case PCM::GRR: @@ -8206,6 +8237,9 @@ void ServerUncorePMUs::initDirect(uint32 socket_, const PCM * pcm) case PCM::SRF: initBHSiMCPMUs(12); break; + case PCM::GNR_D: + initBHSiMCPMUsBase(pcm->getCPUStepping() ? GNR_D_B_MC_CH_PMON_BASE_ADDR : GNR_D_A_MC_CH_PMON_BASE_ADDR, 8); + break; } if (imcPMUs.empty()) @@ -8991,6 +9025,7 @@ void ServerUncorePMUs::programServerUncoreMemoryMetrics(const ServerUncoreMemory } break; case PCM::GNR: + case PCM::GNR_D: case PCM::GRR: case PCM::SRF: if (metrics == PmemMemoryMode) @@ -9087,6 +9122,7 @@ void ServerUncorePMUs::program() EDCCntConfig[EventPosition::WRITE] = MCCntConfig[EventPosition::WRITE] = MC_CH_PCI_PMON_CTL_EVENT(0x05) + MC_CH_PCI_PMON_CTL_UMASK(0xf0); // monitor writes on counter 1: CAS_COUNT.WR break; case PCM::GNR: + case PCM::GNR_D: case PCM::GRR: case PCM::SRF: MCCntConfig[EventPosition::READ] = MC_CH_PCI_PMON_CTL_EVENT(0x05) + MC_CH_PCI_PMON_CTL_UMASK(0xcf); // monitor reads on counter 0: CAS_COUNT_SCH0.RD @@ -9220,6 +9256,7 @@ uint64 ServerUncorePMUs::getImcReadsForChannels(uint32 beginChannel, uint32 endC switch (cpu_family_model) { case PCM::GNR: + case PCM::GNR_D: case PCM::GRR: case PCM::SRF: result += getMCCounter(i, EventPosition::READ2); @@ -9238,6 +9275,7 @@ uint64 ServerUncorePMUs::getImcWrites() switch (cpu_family_model) { case PCM::GNR: + case PCM::GNR_D: case PCM::GRR: case PCM::SRF: result += getMCCounter(i, EventPosition::WRITE2); @@ -9484,6 +9522,7 @@ void ServerUncorePMUs::programM2M() cfg[EventPosition::PMM_WRITE] = M2M_PCI_PMON_CTL_EVENT(0x38) + M2M_PCI_PMON_CTL_UMASK(0x80) + UNC_PMON_CTL_UMASK_EXT(0x1C); // UNC_M2M_IMC_WRITES.TO_PMM break; case PCM::GNR: + case PCM::GNR_D: case PCM::SRF: cfg[EventPosition::NM_HIT] = M2M_PCI_PMON_CTL_EVENT(0x1F) + M2M_PCI_PMON_CTL_UMASK(0x0F); // UNC_B2CMI_TAG_HIT.ALL cfg[EventPosition::M2M_CLOCKTICKS] = 0; // CLOCKTICKS @@ -9962,6 +10001,7 @@ uint64 PCM::CX_MSR_PMON_CTRY(uint32 Cbo, uint32 Ctr) const case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: return SPR_CHA0_MSR_PMON_CTR0 + SPR_CHA_MSR_STEP * Cbo + Ctr; @@ -9994,6 +10034,7 @@ uint64 PCM::CX_MSR_PMON_BOX_FILTER(uint32 Cbo) const case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: return SPR_CHA0_MSR_PMON_BOX_FILTER + SPR_CHA_MSR_STEP * Cbo; @@ -10039,6 +10080,7 @@ uint64 PCM::CX_MSR_PMON_CTLY(uint32 Cbo, uint32 Ctl) const case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: return SPR_CHA0_MSR_PMON_CTL0 + SPR_CHA_MSR_STEP * Cbo + Ctl; @@ -10070,6 +10112,7 @@ uint64 PCM::CX_MSR_PMON_BOX_CTL(uint32 Cbo) const case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: return SPR_CHA0_MSR_PMON_BOX_CTRL + SPR_CHA_MSR_STEP * Cbo; @@ -10144,6 +10187,7 @@ uint32 PCM::getMaxNumOfCBoxesInternal() const { case GRR: case GNR: + case GNR_D: case SRF: { const auto MSR_PMON_NUMBER_CBOS = 0x3fed; @@ -10262,6 +10306,7 @@ void PCM::programIIOCounters(uint64 rawEvents[4], int IIOStack) stacks_count = GRR_M2IOSF_NUM; break; case PCM::GNR: + case PCM::GNR_D: case PCM::SRF: stacks_count = BHS_M2IOSF_NUM; break; @@ -10357,6 +10402,7 @@ void PCM::programPCIeEventGroup(eventGroup_t &eventGroup) switch (cpu_family_model) { case PCM::GNR: + case PCM::GNR_D: case PCM::GRR: case PCM::SRF: case PCM::SPR: @@ -10410,6 +10456,7 @@ void PCM::programCbo(const uint64 * events, const uint32 opCode, const uint32 nc && SPR != cpu_family_model && EMR != cpu_family_model && GNR != cpu_family_model + && GNR_D != cpu_family_model && SRF != cpu_family_model && GRR != cpu_family_model ) @@ -10912,6 +10959,7 @@ void UncorePMU::freeze(const uint32 extra) case PCM::SPR: case PCM::EMR: case PCM::GNR: + case PCM::GNR_D: case PCM::GRR: case PCM::SRF: *unitControl = SPR_UNC_PMON_UNIT_CTL_FRZ; @@ -10928,6 +10976,7 @@ void UncorePMU::unfreeze(const uint32 extra) case PCM::SPR: case PCM::EMR: case PCM::GNR: + case PCM::GNR_D: case PCM::GRR: case PCM::SRF: *unitControl = 0; @@ -10949,6 +10998,7 @@ bool UncorePMU::initFreeze(const uint32 extra, const char* xPICheckMsg) case PCM::SPR: case PCM::EMR: case PCM::GNR: + case PCM::GNR_D: case PCM::GRR: case PCM::SRF: *unitControl = SPR_UNC_PMON_UNIT_CTL_FRZ; // freeze @@ -10989,6 +11039,7 @@ void UncorePMU::resetUnfreeze(const uint32 extra) case PCM::SPR: case PCM::EMR: case PCM::GNR: + case PCM::GNR_D: case PCM::GRR: case PCM::SRF: *unitControl = SPR_UNC_PMON_UNIT_CTL_FRZ + SPR_UNC_PMON_UNIT_CTL_RST_COUNTERS; // freeze and reset counter registers diff --git a/src/cpucounters.h b/src/cpucounters.h index 0e106188..9c395acb 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -1253,6 +1253,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: *ctrl = *curEvent; @@ -2038,6 +2039,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: return (serverUncorePMUs.size() && serverUncorePMUs[0].get()) ? (serverUncorePMUs[0]->getNumQPIPorts()) : 0; @@ -2066,6 +2068,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: case BDX: @@ -2096,6 +2099,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: case BDX: @@ -2129,6 +2133,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: case BDX: @@ -2196,6 +2201,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: return 6; @@ -2250,6 +2256,7 @@ class PCM_API PCM case SPR: case EMR: case GNR: + case GNR_D: case GRR: case SRF: case KNL: @@ -2518,6 +2525,7 @@ class PCM_API PCM || cpu_family_model == PCM::SPR || cpu_family_model == PCM::EMR || cpu_family_model == PCM::GNR + || cpu_family_model == PCM::GNR_D || cpu_family_model == PCM::SRF || cpu_family_model == PCM::GRR ); @@ -2537,6 +2545,7 @@ class PCM_API PCM || cpu_family_model == PCM::SPR || cpu_family_model == PCM::EMR || cpu_family_model == PCM::GNR + || cpu_family_model == PCM::GNR_D || cpu_family_model == PCM::SRF || cpu_family_model == PCM::GRR ); @@ -2625,6 +2634,7 @@ class PCM_API PCM return ( cpu_family_model == PCM::SRF || cpu_family_model == PCM::GNR + || cpu_family_model == PCM::GNR_D ); } @@ -2667,6 +2677,7 @@ class PCM_API PCM || cpu_family_model == PCM::GRR || cpu_family_model == PCM::SRF || cpu_family_model == PCM::GNR + || cpu_family_model == PCM::GNR_D ); } @@ -2676,6 +2687,7 @@ class PCM_API PCM && getMaxNumOfUncorePMUs(UBOX_PMU_ID) > 0ULL && getNumCores() == getNumOnlineCores() && PCM::GNR != cpu_family_model + && PCM::GNR_D != cpu_family_model && PCM::SRF != cpu_family_model ; } @@ -2769,6 +2781,7 @@ class PCM_API PCM || cpu_family_model == PCM::SPR || cpu_family_model == PCM::EMR || cpu_family_model == PCM::GNR + || cpu_family_model == PCM::GNR_D || cpu_family_model == PCM::SRF || cpu_family_model == PCM::GRR || cpu_family_model == PCM::BDX @@ -2816,6 +2829,7 @@ class PCM_API PCM || cpu_family_model == PCM::SPR || cpu_family_model == PCM::EMR || cpu_family_model == PCM::GNR + || cpu_family_model == PCM::GNR_D || cpu_family_model == PCM::SRF || cpu_family_model == PCM::GRR ); @@ -2833,6 +2847,7 @@ class PCM_API PCM || PCM::SPR == cpu_family_model || PCM::EMR == cpu_family_model || PCM::GNR == cpu_family_model + || PCM::GNR_D == cpu_family_model ; } @@ -3548,6 +3563,7 @@ double getDRAMConsumedJoules(const CounterStateType & before, const CounterState || PCM::SKX == cpu_family_model || PCM::ICX == cpu_family_model || PCM::GNR == cpu_family_model + || PCM::GNR_D == cpu_family_model || PCM::SRF == cpu_family_model || PCM::GRR == cpu_family_model || PCM::KNL == cpu_family_model diff --git a/src/opCode-6-174.txt b/src/opCode-6-174.txt new file mode 100644 index 00000000..c3ccfbc9 --- /dev/null +++ b/src/opCode-6-174.txt @@ -0,0 +1,45 @@ +#Clockticks +#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +# Inbound (PCIe device DMA into system) payload events +ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 +ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 +ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 +ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 +ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 +ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 +ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 +ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 +ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 +ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 +ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 +ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 +ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 +ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 +ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 +ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 +ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 +ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 +ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 +ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 +ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 +ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 +ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 +ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 +ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 +ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 +ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 +ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 +ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 +ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 +ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +# IOMMU events +ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total +ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total +ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total +ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total +ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total +ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index f3284b45..c0f03440 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -481,6 +481,14 @@ static const std::string srf_iio_stack_names[] = { "IIO Stack 14 - HCx2 ", // SRF_HC2_PMON_ID 14 }; +const std::string generate_stack_str(const int unit) +{ + static const std::string stack_str = "Stack "; + std::stringstream ss; + ss << stack_str << std::setw(2) << unit; + return ss.str(); +} + struct iio_counter : public counter { std::vector data; }; @@ -736,6 +744,27 @@ class IPlatformMapping { uint32_t cpuId() const { return m_model; } }; +void IPlatformMapping::probeDeviceRange(std::vector &pci_devs, int domain, int secondary, int subordinate) +{ + for (uint8_t bus = secondary; int(bus) <= subordinate; bus++) { + for (uint8_t device = 0; device < 32; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_dev; + child_dev.bdf.domainno = domain; + child_dev.bdf.busno = bus; + child_dev.bdf.devno = device; + child_dev.bdf.funcno = function; + if (probe_pci(&child_dev)) { + if (secondary < child_dev.secondary_bus_number && subordinate < child_dev.subordinate_bus_number) { + probeDeviceRange(child_dev.child_pci_devs, domain, child_dev.secondary_bus_number, child_dev.subordinate_bus_number); + } + pci_devs.push_back(child_dev); + } + } + } + } +} + // Mapping for SkyLake Server. class PurleyPlatformMapping: public IPlatformMapping { private: @@ -756,7 +785,7 @@ void PurleyPlatformMapping::getUboxBusNumbers(std::vector& ubox) pci_dev.bdf.devno = device; pci_dev.bdf.funcno = function; if (probe_pci(&pci_dev)) { - if ((pci_dev.vendor_id == PCM_INTEL_PCI_VENDOR_ID) && (pci_dev.device_id == SKX_SOCKETID_UBOX_DID)) { + if (pci_dev.isIntelDevice() && (pci_dev.device_id == SKX_SOCKETID_UBOX_DID)) { ubox.push_back(bus); } } @@ -847,8 +876,7 @@ bool IPlatformMapping10Nm::getSadIdRootBusMap(uint32_t socket_id, std::map &pci_devs, int domain, int secondary, int subordinate) +class Xeon6thNextGenPlatform: public IPlatformMapping { +private: + bool getRootBuses(std::map> &root_buses); +protected: + virtual bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) = 0; +public: + Xeon6thNextGenPlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} + virtual ~Xeon6thNextGenPlatform() = default; + + bool pciTreeDiscover(std::vector& iios) override; +}; + +bool Xeon6thNextGenPlatform::getRootBuses(std::map> &root_buses) { - for (uint8_t bus = secondary; int(bus) <= subordinate; bus++) { - for (uint8_t device = 0; device < 32; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci child_dev; - child_dev.bdf.domainno = domain; - child_dev.bdf.busno = bus; - child_dev.bdf.devno = device; - child_dev.bdf.funcno = function; - if (probe_pci(&child_dev)) { - if (secondary < child_dev.secondary_bus_number && subordinate < child_dev.subordinate_bus_number) { - probeDeviceRange(child_dev.child_pci_devs, domain, child_dev.secondary_bus_number, child_dev.subordinate_bus_number); + bool mapped = true; + for (uint32_t domain = 0; mapped; domain++) { + mapped = false; + for (uint16_t b = 0; b < 256; b++) { + for (uint8_t d = 0; d < 32; d++) { + for (uint8_t f = 0; f < 8; f++) { + struct pci pci_dev(domain, b, d, f); + if (!probe_pci(&pci_dev)) { + break; + } + if (!(pci_dev.isIntelDevice() && (pci_dev.device_id == SPR_MSM_DEV_ID))) { + continue; + } + + std::uint32_t cpuBusValid; + std::vector cpuBusNo; + int package_id; + + if (!get_cpu_bus(domain, b, d, f, cpuBusValid, cpuBusNo, package_id)) { + return false; + } + + for (int cpuBusId = 0; cpuBusId < SPR_MSM_CPUBUSNO_MAX; ++cpuBusId) { + if (!((cpuBusValid >> cpuBusId) & 0x1)) { + cout << "CPU bus " << cpuBusId << " is disabled on package " << package_id << endl; + continue; + } + int rootBus = (cpuBusNo[(int)(cpuBusId / 4)] >> ((cpuBusId % 4) * 8)) & 0xff; + root_buses[package_id][cpuBusId] = bdf(domain, rootBus, 0, 0); + cout << "Mapped CPU bus #" << cpuBusId << " (domain " << domain << " bus " << std::hex << rootBus << std::dec << ")" + << " package " << package_id << endl; + mapped = true; } - pci_devs.push_back(child_dev); } } } } + return !root_buses.empty(); +} + +bool Xeon6thNextGenPlatform::pciTreeDiscover(std::vector& iios) +{ + std::map> root_buses; + if (!getRootBuses(root_buses)) + { + return false; + } + + for (auto iter = root_buses.cbegin(); iter != root_buses.cend(); ++iter) { + auto rbs_on_socket = iter->second; + struct iio_stacks_on_socket iio_on_socket; + iio_on_socket.socket_id = iter->first; + for (auto rb = rbs_on_socket.cbegin(); rb != rbs_on_socket.cend(); ++rb) { + if (!stackProbe(rb->first, rb->second, iio_on_socket)) { + return false; + } + } + std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); + iios.push_back(iio_on_socket); + } + + return true; } -class BirchStreamPlatform: public IPlatformMapping { +class BirchStreamPlatform: public Xeon6thNextGenPlatform { private: bool isPcieStack(int unit); bool isRootHcStack(int unit); @@ -1669,13 +1754,11 @@ class BirchStreamPlatform: public IPlatformMapping { bool birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); bool birchStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - - bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool getRootBuses(std::map> &root_buses); +protected: + bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) override; public: - BirchStreamPlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} + BirchStreamPlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} ~BirchStreamPlatform() = default; - bool pciTreeDiscover(std::vector& iios) override; }; bool BirchStreamPlatform::birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) @@ -1819,69 +1902,30 @@ bool BirchStreamPlatform::stackProbe(int unit, const struct bdf &address, struct return false; } -bool BirchStreamPlatform::getRootBuses(std::map> &root_buses) -{ - bool mapped = true; - for (uint32_t domain = 0; mapped; domain++) { - mapped = false; - for (uint16_t b = 0; b < 256; b++) { - for (uint8_t d = 0; d < 32; d++) { - for (uint8_t f = 0; f < 8; f++) { - struct pci pci_dev(domain, b, d, f); - if (!probe_pci(&pci_dev)) { - break; - } - if (!((pci_dev.vendor_id == PCM_INTEL_PCI_VENDOR_ID) && (pci_dev.device_id == SPR_MSM_DEV_ID))) { - continue; - } - - std::uint32_t cpuBusValid; - std::vector cpuBusNo; - int package_id; - - if (get_cpu_bus(domain, b, d, f, cpuBusValid, cpuBusNo, package_id) == false) { - return false; - } - - for (int cpuBusId = 0; cpuBusId < SPR_MSM_CPUBUSNO_MAX; ++cpuBusId) { - if (!((cpuBusValid >> cpuBusId) & 0x1)) { - cout << "CPU bus " << cpuBusId << " is disabled on package " << package_id << endl; - continue; - } - int rootBus = (cpuBusNo[(int)(cpuBusId / 4)] >> ((cpuBusId % 4) * 8)) & 0xff; - root_buses[package_id][cpuBusId] = bdf(domain, rootBus, 0, 0); - cout << "Mapped CPU bus #" << cpuBusId << " (domain " << domain << " bus " << std::hex << rootBus << std::dec << ")" - << " package " << package_id << endl; - mapped = true; - } - } - } - } +class KasseyvillePlatform: public Xeon6thNextGenPlatform { +private: + bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool isUboxStack(int unit) + { + return SRF_UBOXA_SAD_BUS_ID == unit || SRF_UBOXB_SAD_BUS_ID == unit; } - return !root_buses.empty(); -} +public: + KasseyvillePlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} + ~KasseyvillePlatform() = default; +}; -bool BirchStreamPlatform::pciTreeDiscover(std::vector& iios) +bool KasseyvillePlatform::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) { - std::map> root_buses; - if (!getRootBuses(root_buses)) - { - return false; - } + // Skip UBOX buses + if (isUboxStack(unit)) return true; - for (auto iter = root_buses.cbegin(); iter != root_buses.cend(); ++iter) { - auto rbs_on_socket = iter->second; - struct iio_stacks_on_socket iio_on_socket; - iio_on_socket.socket_id = iter->first; - for (auto rb = rbs_on_socket.cbegin(); rb != rbs_on_socket.cend(); ++rb) { - if (!stackProbe(rb->first, rb->second, iio_on_socket)) { - return false; - } - } - std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); - iios.push_back(iio_on_socket); - } + // To suppress compilation warning + (void)address; + struct iio_stack stack; + stack.iio_unit_id = unit; + stack.stack_name = generate_stack_str(unit); + iio_on_socket.stacks.push_back(stack); return true; } @@ -1902,6 +1946,9 @@ std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_f case PCM::SRF: case PCM::GNR: return std::unique_ptr{new BirchStreamPlatform(cpu_family_model, sockets_count)}; + case PCM::GNR_D: + std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for Graniterapids-D is provided" << std::endl; + return std::unique_ptr{new KasseyvillePlatform(cpu_family_model, sockets_count)}; default: return nullptr; } @@ -1920,6 +1967,7 @@ ccr* get_ccr(PCM* m, uint64_t& ccr) case PCM::GRR: case PCM::SRF: case PCM::GNR: + case PCM::GNR_D: return new pcm::ccr(ccr, ccr::ccr_type::icx); default: cerr << m->getCPUFamilyModelString() << " is not supported! Program aborted" << endl; diff --git a/src/pcm-memory.cpp b/src/pcm-memory.cpp index 57d373d0..a661fc58 100644 --- a/src/pcm-memory.cpp +++ b/src/pcm-memory.cpp @@ -426,6 +426,7 @@ void printSocketBWFooter(PCM *m, uint32 no_columns, uint32 skt, const memdata_t if ( md->metrics == PartialWrites && m->getCPUFamilyModel() != PCM::SRF && m->getCPUFamilyModel() != PCM::GNR + && m->getCPUFamilyModel() != PCM::GNR_D && m->getCPUFamilyModel() != PCM::GRR ) { @@ -735,6 +736,7 @@ void display_bandwidth_csv(PCM *m, memdata_t *md, uint64 /*elapsedTime*/, const { if ( md->metrics == PartialWrites && m->getCPUFamilyModel() != PCM::GNR + && m->getCPUFamilyModel() != PCM::GNR_D && m->getCPUFamilyModel() != PCM::SRF && m->getCPUFamilyModel() != PCM::GRR ) @@ -996,6 +998,7 @@ void calculate_bandwidth(PCM *m, switch (cpu_family_model) { case PCM::GNR: + case PCM::GNR_D: case PCM::GRR: case PCM::SRF: reads += getMCCounter(channel, ServerUncorePMUs::EventPosition::READ2, uncState1[skt], uncState2[skt]); @@ -1061,6 +1064,7 @@ void calculate_bandwidth(PCM *m, } else if ( cpu_family_model != PCM::GNR + && cpu_family_model != PCM::GNR_D && cpu_family_model != PCM::SRF && cpu_family_model != PCM::GRR ) diff --git a/src/pcm-pcie.cpp b/src/pcm-pcie.cpp index d361d225..79f049d4 100644 --- a/src/pcm-pcie.cpp +++ b/src/pcm-pcie.cpp @@ -97,6 +97,7 @@ IPlatform *IPlatform::getPlatform(PCM *m, bool csv, bool print_bandwidth, bool p { switch (m->getCPUFamilyModel()) { case PCM::GNR: + case PCM::GNR_D: case PCM::SRF: return new BirchStreamPlatform(m, csv, print_bandwidth, print_additional_info, delay); case PCM::GRR: diff --git a/src/types.h b/src/types.h index 9615313c..cbfb6797 100644 --- a/src/types.h +++ b/src/types.h @@ -691,6 +691,8 @@ constexpr auto SERVER_MC_CH_PMON_CTR3_OFFSET = SERVER_MC_CH_PMON_CTR0_OFFSET + 8 constexpr auto SERVER_MC_CH_PMON_FIXED_CTL_OFFSET = 0x54; constexpr auto SERVER_MC_CH_PMON_FIXED_CTR_OFFSET = 0x38; constexpr auto BHS_MC_CH_PMON_BASE_ADDR = 0x024e800; +constexpr auto GNR_D_A_MC_CH_PMON_BASE_ADDR = 0x0104800; +constexpr auto GNR_D_B_MC_CH_PMON_BASE_ADDR = 0x0208800; constexpr auto JKTIVT_QPI_PORT0_REGISTER_DEV_ADDR = 8; constexpr auto JKTIVT_QPI_PORT0_REGISTER_FUNC_ADDR = 2;