AVX2/SVE benchmarks for vector-to-kernels and user option design chan…

…ge (#1002) 1. Add new benchmarks to test `avx2` and `arm sve` instructions set for `vector-to-kernel` lowering, 2. User input option design change for register tiling. Changes the user options from `lhsTile=<x,y> and rhsTile=<y,z>` to `registerBlocking=<x,z>`
libxsmm · Jan 29, 2025 · fecd114 · fecd114
1 parent 8a916d5
commit fecd114
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diff --git a/benchmarks/config/base/base.json b/benchmarks/config/base/base.json
@@ -36,12 +36,26 @@
       "flags": [ "-n", "100" ],
       "extensions": []
     },
-    "gemm_fp32_mlir_vector": {
+    "gemm_fp32_mlir_vector_avx512": {
       "type": "IR-GEN",
       "benchmark": [ "mlir-gen", "--kernel=const --float-type=f32 --batch=256 --layers=1024,1024,1024,1024 --tiles=32,32,32" ],
       "environment": {},
-      "flags": [ "-n", "100",  "-run-args='--vector-to-kernels --lhsTile=4,32 --rhsTile=32,1'" ],
-      "extensions": []
+      "flags": [ "-n", "100",  "-run-args='--vector-to-kernels --registerBlocking=8,32 '" ],
+      "extensions": ["avx512.*"]
+    },
+    "gemm_fp32_mlir_vector_avx2": {
+      "type": "IR-GEN",
+      "benchmark": [ "mlir-gen", "--kernel=const --float-type=f32 --batch=256 --layers=1024,1024,1024,1024 --tiles=32,32,32" ],
+      "environment": {},
+      "flags": [ "-n", "100",  "-run-args='--vector-to-kernels --registerBlocking=4,16 '" ],
+      "extensions": ["avx2"]
+    },
+    "gemm_fp32_mlir_vector_sve": {
+      "type": "IR-GEN",
+      "benchmark": [ "mlir-gen", "--kernel=const --float-type=f32 --batch=256 --layers=1024,1024,1024,1024 --tiles=32,32,32" ],
+      "environment": {},
+      "flags": [ "-n", "100",  "-run-args='--vector-to-kernels --registerBlocking=4,32 '" ],
+      "extensions": ["asimd"]
     },
     "gemm_bf16_dp2_mlir": {
       "type": "IR-GEN",
@@ -64,12 +78,26 @@
       "flags": [ "-n", "100" ],
       "extensions": []
     },
-    "mlp_fp32_mlir_vector": {
+    "mlp_fp32_mlir_vector_avx512": {
       "type": "IR-GEN",
       "benchmark": [ "mlir-gen", "--kernel=const --bias --relu --float-type=f32 --batch=256 --layers=1024,1024,1024,1024 --tiles=32,32,32" ],
       "environment": {},
-      "flags": [ "-n", "100",  "-run-args='--def-parallel --vector-to-kernels --lhsTile=4,32 --rhsTile=32,1'" ],
-      "extensions": []
+      "flags": [ "-n", "100",  "-run-args='--def-parallel --vector-to-kernels --registerBlocking=8,32 '" ],
+      "extensions": ["avx512.*"]
+    },
+    "mlp_fp32_mlir_vector_avx2": {
+      "type": "IR-GEN",
+      "benchmark": [ "mlir-gen", "--kernel=const --bias --relu --float-type=f32 --batch=256 --layers=1024,1024,1024,1024 --tiles=32,32,32" ],
+      "environment": {},
+      "flags": [ "-n", "100",  "-run-args='--def-parallel --vector-to-kernels --registerBlocking=4,16 '" ],
+      "extensions": ["avx2" ]
+    },
+    "mlp_fp32_mlir_vector_sve": {
+      "type": "IR-GEN",
+      "benchmark": [ "mlir-gen", "--kernel=const --bias --relu --float-type=f32 --batch=256 --layers=1024,1024,1024,1024 --tiles=32,32,32" ],
+      "environment": {},
+      "flags": [ "-n", "100",  "-run-args='--def-parallel --vector-to-kernels --registerBlocking=4,32 '" ],
+      "extensions": ["asimd"]
     },
     "mlp_bf16_dp2_mlir": {
       "type": "IR-GEN",
@@ -99,8 +127,8 @@
       "type": "IR-GEN",
       "benchmark": [ "mlir-gen", "--kernel=const --float-type=f32 --batch=256 --layers=1024,1024,1024,1024" ],
       "environment": {},
-      "flags": [ "-n", "100", "-run-args='--vector-to-kernels --lhsTile=4,32 --rhsTile=32,1'" ],
-      "extensions": [ "(avx2|asimd)" ]
+      "flags": [ "-n", "100", "-run-args='--vector-to-kernels --registerBlocking=8,32 '" ],
+      "extensions": [ "avx512.*" ]
     },
     "fp32_3x1024_args_mlir": {
       "type": "IR-GEN",
@@ -113,8 +141,8 @@
       "type": "IR-GEN",
       "benchmark": [ "mlir-gen", "--kernel=args --float-type=f32 --batch=256 --layers=1024,1024,1024,1024" ],
       "environment": {},
-      "flags": [ "-n", "100", "-run-args='--vector-to-kernels --lhsTile=4,32 --rhsTile=32,1'" ],
-      "extensions": [ "(avx2|asimd)" ]
+      "flags": [ "-n", "100", "-run-args='--vector-to-kernels --registerBlocking=8,32 '" ],
+      "extensions": [ "avx512.*" ]
     },
     "bf16_3x1024_const_mlir": {
       "type": "IR-GEN",
@@ -144,8 +172,8 @@
       "type": "IR-GEN",
       "benchmark": [ "mlir-gen", "--kernel=const --bias --relu --float-type=f32 --batch=256 --layers=1024,1024,1024,1024" ],
       "environment": {},
-      "flags": [ "-n", "100", "-run-args='--def-parallel  --vector-to-kernels --lhsTile=4,32 --rhsTile=32,1'" ],
-      "extensions": [ "(avx2|asimd)" ]
+      "flags": [ "-n", "100", "-run-args='--def-parallel  --vector-to-kernels --registerBlocking=8,32 '" ],
+      "extensions": [ "avx512.*" ]
     },
     "fp32_3x1024_args_mlir": {
       "type": "IR-GEN",
@@ -158,8 +186,8 @@
       "type": "IR-GEN",
       "benchmark": [ "mlir-gen", "--kernel=args --bias --relu --float-type=f32 --batch=256 --layers=1024,1024,1024,1024" ],
       "environment": {},
-      "flags": [ "-n", "100", "-run-args=' --def-parallel  --vector-to-kernels --lhsTile=4,32 --rhsTile=32,1'" ],
-      "extensions": [ "(avx2|asimd)" ]
+      "flags": [ "-n", "100", "-run-args=' --def-parallel  --vector-to-kernels --registerBlocking=8,32 '" ],
+      "extensions": [ "avx512.*" ]
     },
     "bf16_3x1024_const_mlir": {
       "type": "IR-GEN",