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Brgemm register tiling for bf16 type #1005

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arun-thmn merged 17 commits into libxsmm:main from arun-thmn:tiling-bf16-support

Feb 19, 2025

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arun-thmn commented Feb 3, 2025 •

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This PR extends the brgemm register tiling pass to support bf16 type. The changes:

Template the existing pass to execute on linalg.batch_reduce_matmul for fp32 and linal.generic for vnni opt bf16,
Test-cases for bf16 type.

Arun Thangamani added 2 commits

January 31, 2025 19:00


          code re-factoring

7943e1e


          code re-factoring and test cases for bf16

310a21a

arun-thmn added the benchmark-full label


          code re-factoring - adding comments, space etc.,.

arun-thmn marked this pull request as ready for review

February 3, 2025 03:38

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arun-thmn commented Feb 3, 2025

@rengolin Request to review this PR for bf16 register tile support. I have re-written the tiling pass with new logic (template and more checks) to tile both fp32 and f16 (vnni). If you have time, I request you to review it as a new pass (as the existing tiling for fp32, I did it immediately joining Intel with lesser understanding of concepts).


          Added a integration test-case for bf16 type

09d9ae7

arun-thmn added benchmark-full and removed benchmark-full labels

rengolin requested review from rolfmorel and adam-smnk

February 5, 2025 00:16

adam-smnk reviewed

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Arun Thangamani added 2 commits

February 12, 2025 22:14


          Added extra validation, made m,n,k tile size as mandatory

ef08d66


          Code re-factoring, changes to test-cases

974c3eb

rengolin reviewed

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rengolin left a comment

I think we need to iterate more on the upstream story later, but if this shows some results, then I'm happy to merge this as soon as @adam-smnk and @rolfmorel are happy with it.

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          Merge remote-tracking branch 'origin' into tiling-bf16-support

59d847a

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          Used upstream code for f32 type and updated unit tests

5d5908c

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Arun Thangamani added 2 commits

February 18, 2025 03:02


          Few re-factoring

ddde637


          With modified tile sizes and interchange options, upstream workd for …

…bf16 vnni

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Arun Thangamani added 2 commits

February 19, 2025 01:46


          tile sizes and interchange options are adjusted with respect to maps

e7682e2


          tile sizes and interchange options are adjusted with respect to maps

0923d3e

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arun-thmn commented Feb 19, 2025 •

edited

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@adam-smnk and @rolfmorel, I have updated the PR. So now with the help of maps and iterator type we choose the tile sizes and tile interchange options. Please have a look.
Also, this PR now can support tensor type as well. I'm plan to do it in a new PR. I need to add few more conditions + alter existing validations.

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          code-refactoring + 1 updated test-case

34e5283

Arun Thangamani added 2 commits

February 19, 2025 06:56


          1 updated test-case for different permutations of affine-map

a178fe2


          minor refactoring tileSizes option

746aa8f

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adam-smnk left a comment

Looks pretty good. Just a few minor comments.

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          validation of parallel count, remove func.func in test-case

f717259

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adam-smnk left a comment

Looks good 👍
Thanks for bearing with all the iterations

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arun-thmn commented Feb 19, 2025 •

edited

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Thanks @adam-smnk and @rolfmorel , it's a good learning for me through your comments. Never did this perfect shaping during college days.


          Merge remote-tracking branch 'origin' into tiling-bf16-support

304bc8c

arun-thmn merged commit f8d8a16 into libxsmm:main

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arun-thmn mentioned this pull request

Brgemm register tiling support for tensor type #1016

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arun-thmn added a commit that referenced this pull request


          Brgemm register tiling support for tensor type (#1016)

0d504c7

This patch extends PR: #1005 to
extend register tiling support for `tensor` type. Also, adds new unit
test-cases.

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