-
Notifications
You must be signed in to change notification settings - Fork 54
/
Copy path0002-RISCV-Recognise-riscv32-and-riscv64-in-triple-parsin.patch
205 lines (198 loc) · 7.74 KB
/
0002-RISCV-Recognise-riscv32-and-riscv64-in-triple-parsin.patch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <[email protected]>
Subject: [RISCV] Recognise riscv32 and riscv64 in triple parsing code
Differential Revision: https://reviews.llvm.org/D23557
Upstream commit: https://reviews.llvm.org/rL285708
---
include/llvm/ADT/Triple.h | 2 ++
lib/Support/Triple.cpp | 21 +++++++++++++++++++++
unittests/ADT/TripleTest.cpp | 36 ++++++++++++++++++++++++++++++++++++
3 files changed, 59 insertions(+)
diff --git a/include/llvm/ADT/Triple.h b/include/llvm/ADT/Triple.h
index 965bd246b83..00fa9c08299 100644
--- a/include/llvm/ADT/Triple.h
+++ b/include/llvm/ADT/Triple.h
@@ -66,6 +66,8 @@ public:
ppc64le, // PPC64LE: powerpc64le
r600, // R600: AMD GPUs HD2XXX - HD6XXX
amdgcn, // AMDGCN: AMD GCN GPUs
+ riscv32, // RISC-V (32-bit): riscv32
+ riscv64, // RISC-V (64-bit): riscv64
sparc, // Sparc: sparc
sparcv9, // Sparcv9: Sparcv9
sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
diff --git a/lib/Support/Triple.cpp b/lib/Support/Triple.cpp
index 9b1a739c911..5062fc43266 100644
--- a/lib/Support/Triple.cpp
+++ b/lib/Support/Triple.cpp
@@ -41,6 +41,8 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
case ppc: return "powerpc";
case r600: return "r600";
case amdgcn: return "amdgcn";
+ case riscv32: return "riscv32";
+ case riscv64: return "riscv64";
case sparc: return "sparc";
case sparcv9: return "sparcv9";
case sparcel: return "sparcel";
@@ -141,6 +143,9 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
case shave: return "shave";
case wasm32:
case wasm64: return "wasm";
+
+ case riscv32:
+ case riscv64: return "riscv";
}
}
@@ -273,6 +278,8 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
.Case("ppc64le", ppc64le)
.Case("r600", r600)
.Case("amdgcn", amdgcn)
+ .Case("riscv32", riscv32)
+ .Case("riscv64", riscv64)
.Case("hexagon", hexagon)
.Case("sparc", sparc)
.Case("sparcel", sparcel)
@@ -398,6 +405,8 @@ static Triple::ArchType parseArch(StringRef ArchName) {
.Case("nios2", Triple::nios2)
.Case("r600", Triple::r600)
.Case("amdgcn", Triple::amdgcn)
+ .Case("riscv32", Triple::riscv32)
+ .Case("riscv64", Triple::riscv64)
.Case("hexagon", Triple::hexagon)
.Cases("s390x", "systemz", Triple::systemz)
.Case("sparc", Triple::sparc)
@@ -647,6 +656,8 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
case Triple::r600:
case Triple::renderscript32:
case Triple::renderscript64:
+ case Triple::riscv32:
+ case Triple::riscv64:
case Triple::shave:
case Triple::sparc:
case Triple::sparcel:
@@ -1185,6 +1196,7 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::nvptx:
case llvm::Triple::ppc:
case llvm::Triple::r600:
+ case llvm::Triple::riscv32:
case llvm::Triple::sparc:
case llvm::Triple::sparcel:
case llvm::Triple::tce:
@@ -1214,6 +1226,7 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::nvptx64:
case llvm::Triple::ppc64:
case llvm::Triple::ppc64le:
+ case llvm::Triple::riscv64:
case llvm::Triple::sparcv9:
case llvm::Triple::systemz:
case llvm::Triple::x86_64:
@@ -1268,6 +1281,7 @@ Triple Triple::get32BitArchVariant() const {
case Triple::nvptx:
case Triple::ppc:
case Triple::r600:
+ case Triple::riscv32:
case Triple::sparc:
case Triple::sparcel:
case Triple::tce:
@@ -1291,6 +1305,7 @@ Triple Triple::get32BitArchVariant() const {
case Triple::nvptx64: T.setArch(Triple::nvptx); break;
case Triple::ppc64: T.setArch(Triple::ppc); break;
case Triple::sparcv9: T.setArch(Triple::sparc); break;
+ case Triple::riscv64: T.setArch(Triple::riscv32); break;
case Triple::x86_64: T.setArch(Triple::x86); break;
case Triple::amdil64: T.setArch(Triple::amdil); break;
case Triple::hsail64: T.setArch(Triple::hsail); break;
@@ -1335,6 +1350,7 @@ Triple Triple::get64BitArchVariant() const {
case Triple::nvptx64:
case Triple::ppc64:
case Triple::ppc64le:
+ case Triple::riscv64:
case Triple::sparcv9:
case Triple::systemz:
case Triple::x86_64:
@@ -1351,6 +1367,7 @@ Triple Triple::get64BitArchVariant() const {
case Triple::nvptx: T.setArch(Triple::nvptx64); break;
case Triple::ppc: T.setArch(Triple::ppc64); break;
case Triple::sparc: T.setArch(Triple::sparcv9); break;
+ case Triple::riscv32: T.setArch(Triple::riscv64); break;
case Triple::x86: T.setArch(Triple::x86_64); break;
case Triple::amdil: T.setArch(Triple::amdil64); break;
case Triple::hsail: T.setArch(Triple::hsail64); break;
@@ -1385,6 +1402,8 @@ Triple Triple::getBigEndianArchVariant() const {
case Triple::nvptx64:
case Triple::nvptx:
case Triple::r600:
+ case Triple::riscv32:
+ case Triple::riscv64:
case Triple::shave:
case Triple::spir64:
case Triple::spir:
@@ -1471,6 +1490,8 @@ bool Triple::isLittleEndian() const {
case Triple::nvptx:
case Triple::ppc64le:
case Triple::r600:
+ case Triple::riscv32:
+ case Triple::riscv64:
case Triple::shave:
case Triple::sparcel:
case Triple::spir64:
diff --git a/unittests/ADT/TripleTest.cpp b/unittests/ADT/TripleTest.cpp
index 93606a98076..c19ad43c723 100644
--- a/unittests/ADT/TripleTest.cpp
+++ b/unittests/ADT/TripleTest.cpp
@@ -295,6 +295,24 @@ TEST(TripleTest, ParsedIDs) {
EXPECT_EQ(Triple::AMDPAL, T.getOS());
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
+ T = Triple("riscv32-unknown-unknown");
+ EXPECT_EQ(Triple::riscv32, T.getArch());
+ EXPECT_EQ(Triple::UnknownVendor, T.getVendor());
+ EXPECT_EQ(Triple::UnknownOS, T.getOS());
+ EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
+
+ T = Triple("riscv64-unknown-linux");
+ EXPECT_EQ(Triple::riscv64, T.getArch());
+ EXPECT_EQ(Triple::UnknownVendor, T.getVendor());
+ EXPECT_EQ(Triple::Linux, T.getOS());
+ EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
+
+ T = Triple("riscv64-unknown-freebsd");
+ EXPECT_EQ(Triple::riscv64, T.getArch());
+ EXPECT_EQ(Triple::UnknownVendor, T.getVendor());
+ EXPECT_EQ(Triple::FreeBSD, T.getOS());
+ EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
+
T = Triple("armv7hl-suse-linux-gnueabi");
EXPECT_EQ(Triple::arm, T.getArch());
EXPECT_EQ(Triple::SUSE, T.getVendor());
@@ -639,6 +657,16 @@ TEST(TripleTest, BitWidthPredicates) {
EXPECT_FALSE(T.isArch16Bit());
EXPECT_TRUE(T.isArch32Bit());
EXPECT_FALSE(T.isArch64Bit());
+
+ T.setArch(Triple::riscv32);
+ EXPECT_FALSE(T.isArch16Bit());
+ EXPECT_TRUE(T.isArch32Bit());
+ EXPECT_FALSE(T.isArch64Bit());
+
+ T.setArch(Triple::riscv64);
+ EXPECT_FALSE(T.isArch16Bit());
+ EXPECT_FALSE(T.isArch32Bit());
+ EXPECT_TRUE(T.isArch64Bit());
}
TEST(TripleTest, BitWidthArchVariants) {
@@ -730,6 +758,14 @@ TEST(TripleTest, BitWidthArchVariants) {
EXPECT_EQ(Triple::wasm32, T.get32BitArchVariant().getArch());
EXPECT_EQ(Triple::wasm64, T.get64BitArchVariant().getArch());
+ T.setArch(Triple::riscv32);
+ EXPECT_EQ(Triple::riscv32, T.get32BitArchVariant().getArch());
+ EXPECT_EQ(Triple::riscv64, T.get64BitArchVariant().getArch());
+
+ T.setArch(Triple::riscv64);
+ EXPECT_EQ(Triple::riscv32, T.get32BitArchVariant().getArch());
+ EXPECT_EQ(Triple::riscv64, T.get64BitArchVariant().getArch());
+
T.setArch(Triple::thumbeb);
EXPECT_EQ(Triple::thumbeb, T.get32BitArchVariant().getArch());
EXPECT_EQ(Triple::aarch64_be, T.get64BitArchVariant().getArch());
--
2.16.2