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TL-UL: bus watchdog #7

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marnovandermaas opened this issue Dec 1, 2023 · 1 comment
Open

TL-UL: bus watchdog #7

marnovandermaas opened this issue Dec 1, 2023 · 1 comment
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@marnovandermaas
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Will there be some kind of bus watchdog to catch invalid accesses or lock ups (missing 'heart beat' signal)? I think this is an important development aid, but it could also be configured to restart the system in the event of a violation being caught and reported by CHERI... rather than just leaving the demo 'IoT system' in a dead state.

Question from @alees24 copied from: #1 (comment)
@marnovandermaas marnovandermaas added the question Further information is requested label Dec 1, 2023
@marnovandermaas marnovandermaas mentioned this issue Dec 4, 2023
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@marnovandermaas
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Similar question applies to the instruction side:
#14 (comment)

At the moment, the logic requires tl_main_pkg::ADDR_MASK_SRAM to be a power of two, it would be good to make it work without that assumption.

@marnovandermaas marnovandermaas mentioned this issue Jan 18, 2024
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