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LR/SC need more tests #375
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Hi! I am also extending tests for LR/SC instructions, in this case with sequences using riscv-dv. My plan would be add a coverpoint at ISA level for LR/SC instructions that also check all possible combinations of aq and rl bits. Also test the following plan: Unaligned/Aligned (riscv_lr_sc_misaligned_instr_stream) Bounded/Non-bounded (riscv_lr_sc_nonbounded_instr_stream) Non-atomic store to same location between pair LR/SC (riscv_lr_sc_invalid_store_instr_stream) Different address pair LR/SC (riscv_lr_sc_invalid_addr_instr_stream) Atomic store to same location between pair LR/SC with diff addr (riscv_lr_sc_invalid_sc_instr_stream) Most recent LR (riscv_lr_sc_recent_lr_instr_stream) |
Hi @franAyachi. This repo is in very active development and isn't ready for casual contributions yet. These tests should be written in the next two months. This isn't really the right forum to do a design review on proposed riscv-dv sequences. If you need these tests and are looking to partner, please email me and we can chat about your needs (find me through my web page, David Harris at Harvey Mudd College). Otherwise, we hope the tests will be more stable by May. |
Systematically check all things that should cancel a reservation, including writes to nearby but not same address, and the list in spec of other things.
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