Not sure how to build Wally for ArtyA7 board

[PietDelaney]

I bought a ArtyA7 board to install Wally but I'm having problems.

I copied the board_files to /tools/Xilinx/Vivado/2024.2/data/boards and
vivado seems to know that I'm trying to build a ArtA7 board but it dies with an error:

   [Synth 8-9263] cannot open include file 'BranchPredictorType.vh' 
                           ["/home/piet/riscv/cvw/fpga/src/CopiedFiles_do_not_add_to_repo/cvw.sv":37]

  [Synth 8-12188] Failed to read verilog '/home/piet/riscv/cvw/fpga/src/CopiedFiles_do_not_add_to_repo/cvw.sv'

 [Common 17-69] Command failed: Vivado Synthesis failed

When I try to let the fpga/generator Makefile handle it there is a different error:

(cvw) piet@piet-Precision-7920-Tower:~/riscv/cvw/fpga/generator$ make
make -C ../../sim deriv
make[1]: Entering directory '/home/piet/riscv/cvw/sim'
derivgen.pl
make[1]: Leaving directory '/home/piet/riscv/cvw/sim'
.
.
.
make[1]: Leaving directory '/home/piet/riscv/cvw/fpga/zsbl'
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log

****** Vivado v2024.2 (64-bit)
**** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024
**** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
**** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
**** Start of session at: Wed Dec 25 22:34:20 2024
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

source wally.tcl

set partNumber $::env(XILINX_PART)

set boardName $::env(XILINX_BOARD)

set boardSubName [lindex [split ${boardName} :] 1]

set board $::env(board)

set ipName WallyFPGA

create_project $ipName . -force -part $partNumber

if {$boardName!="ArtyA7"} {

set_property board_part $boardName [current_project]

}

add_files ../src/CopiedFiles_do_not_add_to_repo/cvw.sv

if {$board=="ArtyA7"} {

add_files {../src/fpgaTopArtyA7.sv}

} else {

add_files {../src/fpgaTop.sv}

}

import_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci

ERROR: [Coretcl 2-1074] Could not find import file 'IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci'
ERROR: [Common 17-69] Command failed: import IP failed in 0 out of 0 cases. See the Messages window for details.

Any tips?

[rosethompson]

It looks like the Xilinx IP is not generated correctly. If you had a bad build which does not produce all the output Xilinx files files (xci, xpr, etc) for each IP the makefile will not always rebuild them. Check that the IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci file exists. If not do make cleanAll to remove all IP. Then try remaking. If you get the same error. Can you provide the log file for IP/sysrst.log. This should explain why it's not building correctly.

[PietDelaney]

Thanks Rose:

Wtih you suggested make cleanAll and rebuilding , the sysrst.xci is being build fine:

    [sysrst.xci.txt](https://github.com/user-attachments/files/18278648/sysrst.xci.txt)

[PietDelaney]

Looks like the fpga make succeeded. I'm building Buildroot and will try to make the flash card with the suggested dev-tree.

Thanks Rose.

[Sriguru840]

Hi,
I want to know if I can use only the core part of core v wally as top module and verify using this testbench. Not sure it can be done or not.
What are all changes should be made?
Thanks.

[davidharrishmc]

You can do whatever you want, but the Wally team can only support the standard flow.

…

On Jan 24, 2025, at 2:04 AM, Sriguru840 ***@***.***> wrote: Hi, I want to know if I can use only the core part of core v wally as top module and verify using this testbench. Not sure it can be done or not. What are all changes should be made? Thanks. — Reply to this email directly, view it on GitHub <#1207 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA33ITYU2FRD3PCYYP2L2MIF2FAVCNFSM6AAAAABUGZTRNGVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTCOJUGE2DQMQ>. You are receiving this because you are subscribed to this thread.