animated-shapes

Animated Shapes

This folder accompanies the Project F blog post: Animated Shapes. These SystemVerilog designs animate shapes using a double-buffered framebuffer. You can freely build on these MIT licensed designs. Have fun.

File layout:

• 160x90 - render modules for 160x90 with 4 colours
• 320x180 - render modules for 320x180 with 16 colours
• ice40 - designs for iCEBreaker and other Lattice iCE40 boards
• sim - simulation with Verilator and LibSDL; see the Simulation README
• xc7 - designs for Arty and other Xilinx 7 Series boards with VGA output
• xc7-dvi - designs for Nexys Video and other Xilinx 7 Series boards with DVI output

These designs make use of modules from the Project F library. Check the included iCE40 Makefile or Vivado create_project.tcl to see the list of modules.

There is are two demo top module that can draw different things:

• top_demo_sb - single buffer animation without screen clear
• top_demo double buffer animation with screen clear

To switch between the different demos, change the render instance near line 155 in top_demo or line 100 in top_demo_sb:

• render_square_colr - colour-cycling square bounces around the screen
• render_cube_shatter - shatter 3D cube drawn from six triangles
• render_teleport - teleport effect with nested squares

Learn more about the designs and demos from the Animated Shapes blog post, or read on for build instructions. New to graphics development on FPGA? Check out Beginning FPGA Graphics.

Bouncing square drawn by an Artix-7 FPGA.

iCEBreaker Build

You can build projects for iCEBreaker using the included Makefile with Yosys, nextpnr, and IceStorm Tools.

You can get pre-built tool binaries for Linux, Mac, and Windows from YosysHQ. If you want to build the tools yourself, check out Building iCE40 FPGA Toolchain on Linux.

To build the demo project, clone the projf-explore git repo, then:

cd projf-explore/graphics/animated-shapes/ice40
make demo

After the build completes, you'll have a bin file called demo.bin. Use the bin file to program your board:

iceprog demo.bin

If you get the error Can't find iCE FTDI USB device, try running iceprog with sudo.

For the single buffer version, replace demo with demo_sb in the above instructions.

Problems Building

If Yosys reports "syntax error, unexpected TOK_ENUM", then your version is too old to support Project F designs. Try building the latest version of Yosys from source (see above for links).

Arty Build

To create a Vivado project for the Digilent Arty (original or A7-35T); clone the projf-explore git repo, then start Vivado and run the following in the Tcl console:

cd projf-explore/animated-shapes/xc7/vivado
source ./create_project.tcl

You can then build top_demo and top_demo_sb as you would for any Vivado project.

Other Xilinx 7 Series Boards

It's straightforward to adapt the project for other Xilinx 7 Series boards:

1. Create a suitable constraints file named <board>.xdc within the xc7 directory
2. Make a note of your board's FPGA part, such as xc7a35ticsg324-1L
3. Set the board and part names in Tcl, then source the create project script:

set board_name <board>
set fpga_part <fpga-part>
cd projf-explore/animated-shapes/xc7/vivado
source ./create_project.tcl

Replace <board> and <fpga-part> with the actual board and part names.

Nexys Video Build

To create a Vivado project for the Digilent Nexys Video; clone the projf-explore git repo, then start Vivado and run the following in the Tcl console:

cd projf-explore/graphics/animated-shapes/xc7-dvi/vivado
source ./create_project.tcl

You can then build top_demo and top_demo_sb as you would for any Vivado project.

Tested Versions

The Nexys Video designs have been tested with:

• Vivado 2022.2

Verilator SDL Simulation

You can simulate these designs on your computer using Verilator and SDL. The Simulation README has build instructions.

Linting

If you have Verilator installed, you can run the linting shell script lint.sh to check the designs. Learn more from Verilog Lint with Verilator.

SystemVerilog?

These designs use a little SystemVerilog to make Verilog more pleasant. See the Library README for details of SV features used.