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Graphics - Verilog Library

Graphics Verilog designs from Project F, including line and shape drawing. You can freely build on these MIT licensed designs. Get an overview of the whole lib from the Verilog Library blog.

Verilog Modules

Locate Vivado test benches in the xc7 directory.
For modules to drive a display, see display.
Find other modules in the Library.

Blog Posts

The following blog posts document and make use of these graphics designs:

Graphics Modules Interface

These graphic modules share a similar interface:

  • input: clk - clock
  • input: rst - synchronous reset (active high)
  • input: start - start drawing (if currently idle)
  • input: oe - output enable (allows drawing to be paused)
  • input: (x0,y0) - vertex 0
  • input: (x1,y1) - vertex 1
  • input: (x2,y2) - vertex 2 (used by triangles)
  • input: r0 - radius (used by circles)
  • input: ucp - Unicode code point (used by text)
  • output: (x,y) - output drawing coordinate
  • output: drawing - graphics are being drawn at (x,y)
  • output: busy - drawing request in progress
  • output: done - drawing is complete (high for one tick)

Graphics coordinates are signed, with a width in bits set by parameter CORDW.
The default coordinate width is 16 bits for a range from -32,768 to 32,767.

Drawing order or direction may differ from the order coordinates are given; for example, drawing doesn't necesserily begin from (x0,y0).

SystemVerilog?

These modules use a little SystemVerilog to make Verilog more pleasant, see the main Library README for details.