Getting Testbench To Work

[AdeAdeRH]

I have worked through quite a few of the excellent projects, which are informative and most helpful.

In Vivado I am creating a new project and adding, for example, Design Sources for "top_bounce.sv", "clock_480p.sv" and "simple_480p.sv". I am also adding the constraints file "arty.xdc". Everything works fine and I can create the Bitstream file and program the arty a7-35.

If I then add the testbench file "simple_480p_tb.sv" to the simulation sources in the project manager (seperate from the design sources), make this the top file in the list and execute the testbench file by clicking "Run Simulation", I get results as shown in the below screenshot.

However, if I follow the instructions to clone the "projf-explore" files and in the tcl console in Vivado enter:

cd projf-explore/graphics/fpga-graphics/xc7/vivado
source ./create_project.tcl

And

launch_simulation
run all

The "simple_480p_tb.sv" testbench runs as shown in the tutorial / blog.

It would be most helpful if you could please advise where I am going wrong.

[WillGreen]

Hello,

I don’t think you’re doing anything wrong.

If you look at the timescale at the top of the waveform viewer, it’s only showing the first 1000 ns. You need to run the simulation for longer, so the clocks have time to settle down. Try hitting the green play button to run the simulation longer (it stops at 1000 ns by default).

You can zoom out of the simulation to see more time using the magnifying glass icon near the top left of the waveform viewer.

I hope that helps.

[AdeAdeRH]

Found the RUN button and it all works fine (easy when you know how)

Thanks again Will for the help

[WillGreen]

I’m glad you got it working. I had similar issues when I started out with Vivado.

[AdeAdeRH]

The "Simple Display Test Bench" is written in system verilog

I have previously been working in verilog and would like to switch to system verilog but i am trying understand how to convert between the two.

It would be a big help if someone could provide the "Simple Display Test Bench" re-written in verilog

[WillGreen]

I'm not planning to create separate versions of my designs without SystemVerilog features.

The good news is that the SV features Project F uses are minimal and straightforward: see SystemVerilog in the README for a list.

[AdeAdeRH]

Thanks Will, thats my plan not to write in verilog but to change to systemverilog. This means rewriting some code i have in verilog to systemverilog. Just finding it difficult but will try your suggestion.

[WillGreen]

Good luck. If you get stuck on something specific, feel free to ask.