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Anthony Liguori
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Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into staging
xtensa queue 2013-07-29 * filippov/tags/20130729-xtensa: target-xtensa: check register window inline target-xtensa: don't generate dead code to access invalid SRs tests/tcg/xtensa: Fix out-of-tree build target-xtensa: avoid double-stopping at breakpoints target-xtensa: add fallthrough markers target-xtensa: add extui unit test Conflicts: configure Signed-off-by: Anthony Liguori <[email protected]>
2 parents 144f28f + 908c67f commit 64160cd

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6 files changed

+93
-34
lines changed

6 files changed

+93
-34
lines changed

‎configure

+2-2
Original file line numberDiff line numberDiff line change
@@ -4507,13 +4507,13 @@ if [ "$dtc_internal" = "yes" ]; then
45074507
fi
45084508

45094509
# build tree in object directory in case the source is not in the current directory
4510-
DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32 tests/libqos tests/qapi-schema"
4510+
DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32 tests/libqos tests/qapi-schema tests/tcg/xtensa"
45114511
DIRS="$DIRS pc-bios/optionrom pc-bios/spapr-rtas pc-bios/s390-ccw"
45124512
DIRS="$DIRS roms/seabios roms/vgabios"
45134513
DIRS="$DIRS qapi-generated"
45144514
FILES="Makefile tests/tcg/Makefile qdict-test-data.txt"
45154515
FILES="$FILES tests/tcg/cris/Makefile tests/tcg/cris/.gdbinit"
4516-
FILES="$FILES tests/tcg/lm32/Makefile po/Makefile"
4516+
FILES="$FILES tests/tcg/lm32/Makefile tests/tcg/xtensa/Makefile po/Makefile"
45174517
FILES="$FILES pc-bios/optionrom/Makefile pc-bios/keymaps"
45184518
FILES="$FILES pc-bios/spapr-rtas/Makefile"
45194519
FILES="$FILES pc-bios/s390-ccw/Makefile"

‎target-xtensa/cpu.h

+4
Original file line numberDiff line numberDiff line change
@@ -484,6 +484,7 @@ static inline int cpu_mmu_index(CPUXtensaState *env)
484484
#define XTENSA_TBFLAG_ICOUNT 0x20
485485
#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
486486
#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
487+
#define XTENSA_TBFLAG_EXCEPTION 0x4000
487488

488489
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
489490
target_ulong *cs_base, int *flags)
@@ -510,6 +511,9 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
510511
if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
511512
*flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
512513
}
514+
if (ENV_GET_CPU(env)->singlestep_enabled && env->exception_taken) {
515+
*flags |= XTENSA_TBFLAG_EXCEPTION;
516+
}
513517
}
514518

515519
#include "exec/cpu-all.h"

‎target-xtensa/op_helper.c

+5
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,9 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
9696
void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
9797
{
9898
env->exception_index = excp;
99+
if (excp == EXCP_DEBUG) {
100+
env->exception_taken = 0;
101+
}
99102
cpu_loop_exit(env);
100103
}
101104

@@ -448,8 +451,10 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
448451
switch (access & PAGE_CACHE_MASK) {
449452
case PAGE_CACHE_WB:
450453
atomctl >>= 2;
454+
/* fall through */
451455
case PAGE_CACHE_WT:
452456
atomctl >>= 2;
457+
/* fall through */
453458
case PAGE_CACHE_BYPASS:
454459
if ((atomctl & 0x3) == 0) {
455460
HELPER(exception_cause_vaddr)(env, pc,

‎target-xtensa/translate.c

+44-23
Original file line numberDiff line numberDiff line change
@@ -305,16 +305,21 @@ static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
305305
tcg_temp_free(tmp);
306306
}
307307

308-
static void gen_advance_ccount(DisasContext *dc)
308+
static void gen_advance_ccount_cond(DisasContext *dc)
309309
{
310310
if (dc->ccount_delta > 0) {
311311
TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
312-
dc->ccount_delta = 0;
313312
gen_helper_advance_ccount(cpu_env, tmp);
314313
tcg_temp_free(tmp);
315314
}
316315
}
317316

317+
static void gen_advance_ccount(DisasContext *dc)
318+
{
319+
gen_advance_ccount_cond(dc);
320+
dc->ccount_delta = 0;
321+
}
322+
318323
static void reset_used_window(DisasContext *dc)
319324
{
320325
dc->used_window = 0;
@@ -491,7 +496,7 @@ static void gen_brcondi(DisasContext *dc, TCGCond cond,
491496
tcg_temp_free(tmp);
492497
}
493498

494-
static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
499+
static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
495500
{
496501
if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
497502
if (sregnames[sr].name) {
@@ -500,6 +505,7 @@ static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
500505
qemu_log("SR %d is not implemented\n", sr);
501506
}
502507
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
508+
return false;
503509
} else if (!(sregnames[sr].access & access)) {
504510
static const char * const access_text[] = {
505511
[SR_R] = "rsr",
@@ -510,7 +516,9 @@ static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
510516
qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
511517
access_text[access]);
512518
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
519+
return false;
513520
}
521+
return true;
514522
}
515523

516524
static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
@@ -826,15 +834,27 @@ static void gen_window_check1(DisasContext *dc, unsigned r1)
826834
}
827835
if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
828836
r1 / 4 > dc->used_window) {
829-
TCGv_i32 pc = tcg_const_i32(dc->pc);
830-
TCGv_i32 w = tcg_const_i32(r1 / 4);
837+
int label = gen_new_label();
838+
TCGv_i32 ws = tcg_temp_new_i32();
831839

832840
dc->used_window = r1 / 4;
833-
gen_advance_ccount(dc);
834-
gen_helper_window_check(cpu_env, pc, w);
841+
tcg_gen_deposit_i32(ws, cpu_SR[WINDOW_START], cpu_SR[WINDOW_START],
842+
dc->config->nareg / 4, dc->config->nareg / 4);
843+
tcg_gen_shr_i32(ws, ws, cpu_SR[WINDOW_BASE]);
844+
tcg_gen_andi_i32(ws, ws, (2 << (r1 / 4)) - 2);
845+
tcg_gen_brcondi_i32(TCG_COND_EQ, ws, 0, label);
846+
{
847+
TCGv_i32 pc = tcg_const_i32(dc->pc);
848+
TCGv_i32 w = tcg_const_i32(r1 / 4);
849+
850+
gen_advance_ccount_cond(dc);
851+
gen_helper_window_check(cpu_env, pc, w);
835852

836-
tcg_temp_free(w);
837-
tcg_temp_free(pc);
853+
tcg_temp_free(w);
854+
tcg_temp_free(pc);
855+
}
856+
gen_set_label(label);
857+
tcg_temp_free(ws);
838858
}
839859
}
840860

@@ -1482,9 +1502,9 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
14821502
break;
14831503

14841504
case 6: /*XSR*/
1485-
{
1505+
if (gen_check_sr(dc, RSR_SR, SR_X)) {
14861506
TCGv_i32 tmp = tcg_temp_new_i32();
1487-
gen_check_sr(dc, RSR_SR, SR_X);
1507+
14881508
if (RSR_SR >= 64) {
14891509
gen_check_privilege(dc);
14901510
}
@@ -1707,21 +1727,23 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
17071727
case 3: /*RST3*/
17081728
switch (OP2) {
17091729
case 0: /*RSR*/
1710-
gen_check_sr(dc, RSR_SR, SR_R);
1711-
if (RSR_SR >= 64) {
1712-
gen_check_privilege(dc);
1730+
if (gen_check_sr(dc, RSR_SR, SR_R)) {
1731+
if (RSR_SR >= 64) {
1732+
gen_check_privilege(dc);
1733+
}
1734+
gen_window_check1(dc, RRR_T);
1735+
gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
17131736
}
1714-
gen_window_check1(dc, RRR_T);
1715-
gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
17161737
break;
17171738

17181739
case 1: /*WSR*/
1719-
gen_check_sr(dc, RSR_SR, SR_W);
1720-
if (RSR_SR >= 64) {
1721-
gen_check_privilege(dc);
1740+
if (gen_check_sr(dc, RSR_SR, SR_W)) {
1741+
if (RSR_SR >= 64) {
1742+
gen_check_privilege(dc);
1743+
}
1744+
gen_window_check1(dc, RRR_T);
1745+
gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
17221746
}
1723-
gen_window_check1(dc, RRR_T);
1724-
gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
17251747
break;
17261748

17271749
case 2: /*SEXTu*/
@@ -2918,8 +2940,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
29182940

29192941
gen_tb_start();
29202942

2921-
if (cs->singlestep_enabled && env->exception_taken) {
2922-
env->exception_taken = 0;
2943+
if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
29232944
tcg_gen_movi_i32(cpu_pc, dc.pc);
29242945
gen_exception(&dc, EXCP_DEBUG);
29252946
}

‎tests/tcg/xtensa/Makefile

+12-9
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
-include ../../config-host.mak
1+
-include ../../../config-host.mak
22

33
CROSS=xtensa-dc232b-elf-
44

55
ifndef XT
6-
SIM = qemu-system-xtensa
6+
SIM = ../../../xtensa-softmmu/qemu-system-xtensa
77
SIMFLAGS = -M sim -cpu dc232b -nographic -semihosting $(EXTFLAGS) -kernel
88
SIMDEBUG = -s -S
99
else
@@ -13,10 +13,12 @@ SIMDEBUG = --gdbserve=0
1313
endif
1414

1515
CC = $(CROSS)gcc
16-
AS = $(CROSS)gcc -x assembler
16+
AS = $(CROSS)gcc -x assembler-with-cpp
1717
LD = $(CROSS)ld
1818

19-
LDFLAGS = -Tlinker.ld
19+
XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa
20+
21+
LDFLAGS = -T$(XTENSA_SRC_PATH)/linker.ld
2022

2123
CRT = crt.o vectors.o
2224

@@ -26,6 +28,7 @@ TESTCASES += test_bi.tst
2628
TESTCASES += test_break.tst
2729
TESTCASES += test_bz.tst
2830
TESTCASES += test_clamps.tst
31+
TESTCASES += test_extui.tst
2932
TESTCASES += test_fail.tst
3033
TESTCASES += test_interrupt.tst
3134
TESTCASES += test_loop.tst
@@ -52,13 +55,13 @@ TESTCASES += test_windowed.tst
5255

5356
all: build
5457

55-
%.o: $(SRC_PATH)/tests/xtensa/%.c
56-
$(CC) $(CFLAGS) -c $< -o $@
58+
%.o: $(XTENSA_SRC_PATH)/%.c
59+
$(CC) -I$(XTENSA_SRC_PATH) $(CFLAGS) -c $< -o $@
5760

58-
%.o: $(SRC_PATH)/tests/xtensa/%.S
59-
$(AS) $(ASFLAGS) -c $< -o $@
61+
%.o: $(XTENSA_SRC_PATH)/%.S
62+
$(AS) -Wa,-I,$(XTENSA_SRC_PATH) $(ASFLAGS) -c $< -o $@
6063

61-
%.tst: %.o macros.inc $(CRT) Makefile
64+
%.tst: %.o $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
6265
$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@
6366

6467
build: $(TESTCASES)

‎tests/tcg/xtensa/test_extui.S

+26
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
.include "macros.inc"
2+
3+
test_suite extui
4+
5+
.macro test_extui v, shiftimm, maskimm
6+
.if \shiftimm + \maskimm <= 32
7+
movi a2, \v
8+
extui a3, a2, \shiftimm, \maskimm
9+
movi a4, ((\v) >> (\shiftimm)) & ((1 << (\maskimm)) - 1)
10+
assert eq, a3, a4
11+
.endif
12+
.endm
13+
14+
test extui
15+
.set shiftimm, 0
16+
.rept 32
17+
.set maskimm, 1
18+
.rept 16
19+
test_extui 0xc8df1370, shiftimm, maskimm
20+
.set maskimm, maskimm + 1
21+
.endr
22+
.set shiftimm, shiftimm + 1
23+
.endr
24+
test_end
25+
26+
test_suite_end

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