Synch with N5_SoC

Author: shalan

README.md

@@ -1,3 +1,25 @@
-# Chameleon SoC
+# Chameleon SoC (IBEX)
 AHB-Lite based SoC for IBEX
 
+## The Memory Map
+<img src="./docs/soc_mem_map.png" size="50%">
+
+## Peripherals
+|Peripheral|Bus|Base Address|IRQ #|MPRJ I/O Pins|
+|----------|---|------------|--------|-----|
+|GPIO (14)|AHB|0x48000000|N/A|0-13|
+|UART0|APB|0x40000000|16|20-21|
+|UART1|APB|0x40100000|17|22-23|
+|SPI0|APB|0x40200000|18|24-27|
+|SPI1|APB|0x40300000|19|28-31|
+|I2C0|APB|0x40400000|20|32-33|
+|I2C1|APB|0x40500000|21|34-35|
+|PWM0|APB|0x40600000|n/a|26|
+|PWM1|APB|0x40700000|n/a|37|
+|TMR0|APB|0x40800000|22|n/a|
+|TMR1|APB|0x40900000|23|n/a|
+|TMR2|APB|0x40A00000|24|n/a|
+|TMR3|APB|0x40B00000|25|n/a|
+|WDT0|APB|0x40C00000|26|n/a|
+|WDT1|APB|0x40D00000|27|n/a|
+

docs/soc_mem_map.png

@@ -0,0 +1,32 @@
+module DFFRAM_beh #( parameter COLS=1)
+(
+    CLK,
+    WE,
+    EN,
+    Di,
+    Do,
+    A
+);
+    localparam A_WIDTH = 8+$clog2(COLS);
+
+    input   wire            CLK;
+    input   wire    [3:0]   WE;
+    input   wire            EN;
+    input   wire    [31:0]  Di;
+    output  reg     [31:0]  Do;
+    input   wire    [(A_WIDTH - 1): 0]   A;
+
+    reg [31:0] RAM[(256*COLS)-1 : 0];
+    
+    always @(posedge CLK) 
+        if(EN) begin
+            Do <= RAM[A];
+            if(WE[0]) RAM[A][ 7: 0] <= Di[7:0];
+            if(WE[1]) RAM[A][15:8] <= Di[15:8];
+            if(WE[2]) RAM[A][23:16] <= Di[23:16];
+            if(WE[3]) RAM[A][31:24] <= Di[31:24];
+        end 
+        else
+            Do <= 32'b0;
+            
+endmodule

dv/23LC512.v

@@ -1,10 +1,10 @@
 `timescale 1ns/1ns
 
 `define   TEST_FILE   "../sw/test.hex" 
-`define   SIM_TIME    100_000
-`define   SIM_LEVEL   4
+`define   SIM_TIME    800_000
+`define   SIM_LEVEL   0
 
-module Chameleon_SoC_TB;
+module IBEX_SoC_TB;
 
     reg HCLK, HRESETn;
 
@@ -52,6 +52,10 @@ module Chameleon_SoC_TB;
     wire [0: 0] sda_o_Sys0_SS0_S5;
     wire [0: 0] sda_oen_o_Sys0_SS0_S5;
 
+    wire [0: 0] pwm_Sys0_SS0_S6;
+	wire [0: 0] pwm_Sys0_SS0_S7;
+
+    /* Program Flash */
     assign fdio = fdoe ? fdo : 4'bzzzz;
     assign fdi = fdio;
 
@@ -65,9 +69,9 @@ module Chameleon_SoC_TB;
         .HCLK(HCLK),
         .HRESETn(HRESETn),
 
-        //input [7: 0] Input_DATA,
-        //input [0: 0] Input_irq,
-        //output Output_DATA,
+        .SYSTICKCLKDIV(8'd100),
+        .NMI(1'b0),
+       
         .fdi_Sys0_S0(fdi),
         .fdo_Sys0_S0(fdo),
         .fdoe_Sys0_S0(fdoe),
@@ -82,12 +86,10 @@ module Chameleon_SoC_TB;
 
         .RsRx_Sys0_SS0_S0(RsRx_Sys0_SS0_S0),
         .RsTx_Sys0_SS0_S0(RsTx_Sys0_SS0_S0),
-        //output wire [0: 0] uart_irq_Sys0_SS0_S0,
 
         .RsRx_Sys0_SS0_S1(RsRx_Sys0_SS0_S1),
         .RsTx_Sys0_SS0_S1(RsTx_Sys0_SS0_S1),
-        //output wire [0: 0] uart_irq_Sys0_SS0_S1,
-      
+       
         .MSI_Sys0_SS0_S2(MSI_Sys0_SS0_S2),
         .MSO_Sys0_SS0_S2(MSO_Sys0_SS0_S2),
         .SSn_Sys0_SS0_S2(SSn_Sys0_SS0_S2),
@@ -110,14 +112,39 @@ module Chameleon_SoC_TB;
         .scl_oen_o_Sys0_SS0_S5(scl_oen_o_Sys0_SS0_S5),
         .sda_i_Sys0_SS0_S5(sda_i_Sys0_SS0_S5),
         .sda_o_Sys0_SS0_S5(sda_o_Sys0_SS0_S5),
-        .sda_oen_o_Sys0_SS0_S5(sda_oen_o_Sys0_SS0_S5)
-/*
-        output wire [0: 0] pwm_Sys0_SS0_S6,
-        output wire [0: 0] pwm_Sys0_SS0_S7 */
-        //.db_reg_Sys0(db_reg_Sys0)
+        .sda_oen_o_Sys0_SS0_S5(sda_oen_o_Sys0_SS0_S5),
+
+        .pwm_Sys0_SS0_S6(pwm_Sys0_SS0_S6),
+	    .pwm_Sys0_SS0_S7(pwm_Sys0_SS0_S7)
+
     );
 
-// Load the application into the flash memory
+    // GPIO Loopback!
+    wire [15:0] GPIO_PINS;
+    generate
+        genvar i;
+        for(i=0; i<16; i=i+1)
+            assign GPIO_PINS[i] = GPIOOEN_Sys0_S2[i] ? GPIOOUT_Sys0_S2[i] : 1'bz;
+    endgenerate
+    assign GPIO_PINS[15:8] = GPIO_PINS[7:0];
+    assign GPIOIN_Sys0_S2 = GPIO_PINS;
+
+
+    // Serial Terminal connected to UART0 TX*/
+    terminal term(.rx(RsTx_Sys0_SS0_S0));
+
+    // SPI SRAM connected to SPI0
+    wire SPI_HOLD = 1'b1;
+    M23LC512 SPI_SRAM(
+        .RESET(~HRESETn),
+        .SO_SIO1(MSI_Sys0_SS0_S2),
+        .SI_SIO0(MSO_Sys0_SS0_S2),
+        .CS_N(SSn_Sys0_SS0_S2),
+        .SCK(SCLK_Sys0_SS0_S2),
+        .HOLD_N_SIO3(SPI_HOLD)
+	);
+
+    // Load the application into the flash memory
     initial begin
         #1  $readmemh(`TEST_FILE, flash.I0.memory);
     end
@@ -138,28 +165,29 @@ module Chameleon_SoC_TB;
 
     // Dump file
     initial begin
-        $dumpfile("Chameleon_SoC_TB.vcd");
-        $dumpvars(`SIM_LEVEL, Chameleon_SoC_TB);
+        $dumpfile("IBEX_SoC_TB.vcd");
+        $dumpvars(`SIM_LEVEL, IBEX_SoC_TB);
         #`SIM_TIME;
         $finish;
     end
 
     // Terminate the smulation with ebreak instruction.
     // Calculate the CPI using the CSRs
-    //always @ (posedge HCLK) 
-        //if(MUV.CPU.N5.instr_ebreak) begin
+    /*
+    always @ (posedge HCLK) 
+        if(MUV.CPU.N5.instr_ebreak) begin
         //$display("CPI=%d.%0d", MUV.N5.CSR_CYCLE/MUV.N5.CSR_INSTRET,(MUV.N5.CSR_CYCLE%MUV.N5.CSR_INSTRET)*10/MUV.N5.CSR_INSTRET );
-        //$finish;
-        //end
-
+        $finish;
+        end
+    */
 
     // Monitor Flash memory reads
     //always @(posedge HCLK)
     //    if(MUV.N5.HTRANS[1] & MUV.N5.HREADY & MUV.N5.HSEL_FLASH)
     //    $display("Flash Read A:%X (%0t)", HADDR, $time);
 
 
-    terminal term(.rx(RsTx_Sys0_SS0_S0));
+    
 endmodule
 
 module terminal #(parameter bit_time = 160) (input rx);

dv/DFFRAM_beh.v

@@ -7,9 +7,14 @@ test.hex: ../sw/test.c ../sw/crt0.S ../sw/link.ld
 test.vvp: test.hex files.list
 	iverilog -o test.vvp -D TEST_FIL="../sw/test.hex" -c files.list
 
-sim: test.vvp
+test_fast.vvp: test.hex files_fast_sim.list
+	iverilog -o test_fast.vvp -D TEST_FIL="../sw/test.hex" -c files_fast_sim.list
+
+sim: test.vvp 
 	./test.vvp
 
+sim_fast: test_fast.vvp 
+	./test_fast.vvp
 
 clean:
 	rm *.vvp

dv/Chameleon_SoC_TB.v dv/IBEX_SoC_TB.v

@@ -24,10 +24,17 @@
 ../rtl/IPs/APB_UART.v
 ../rtl/IPs/APB_SPI.v
 ../rtl/IPs/APB_I2C.v
-../rtl/IPs/DFFRAM.v
-../rtl/IPs/DFFRAMBB.v
+../dv/DFFRAM_beh.v
++define+HC_CACHE=1
 ../rtl/IPs/QSPI_XIP_CTRL.v
 ../rtl/IPs/AHBSRAM.v
+../rtl/IPs/DFFRAM.v
+../rtl/IPs/DFFRAMBB.v
+../rtl/IPs/RAM_3Kx32.v
+../rtl/acc/AHB_SPM.v
+
+#+define+USE_DFFRAM_BEH=1
+../rtl/soc_core.v
 
 ../rtl/ibex/ibex_wrapper.v
 ../rtl/ibex/ibex_alu.v
@@ -55,8 +62,6 @@
 ../rtl/ibex/prim_clock_gating.v 
 ../rtl/ibex/ibex_register_file_ff.v
 
-
-Chameleon_SoC_TB.v
+IBEX_SoC_TB.v
 sst26wf080b.v
-../rtl/soc_core.v
-../rtl/DFFRFile.v 
+23LC512.v 

dv/Makefile

@@ -0,0 +1,70 @@
+../pdk/hd_primitives.v 
+../pdk/hd_functional.v
+
+../rtl/AHB_sys_0/AHBlite_sys_0.v 
+../rtl/AHB_sys_0/AHBlite_bus0.v
+../rtl/AHB_sys_0/AHBlite_GPIO.v
+../rtl/AHB_sys_0/AHBlite_db_reg.v
+
+#-y ../rtl/AHB_sys_0/APB_sys_0/
+../rtl/AHB_sys_0/APB_sys_0/APB_WDT32.v
+../rtl/AHB_sys_0/APB_sys_0/APB_TIMER32.v
+../rtl/AHB_sys_0/APB_sys_0/APB_PWM32.v
+../rtl/AHB_sys_0/APB_sys_0/AHB_2_APB.v
+../rtl/AHB_sys_0/APB_sys_0/APB_bus0.v
+../rtl/AHB_sys_0/APB_sys_0/APB_sys_0.v
+
+#-y ../rtl/IPs
+../rtl/IPs/TIMER32.v
+../rtl/IPs/PWM32.v
+../rtl/IPs/WDT32.v
+../rtl/IPs/spi_master.v
+../rtl/IPs/i2c_master.v
+../rtl/IPs/GPIO.v
+../rtl/IPs/APB_UART.v
+../rtl/IPs/APB_SPI.v
+../rtl/IPs/APB_I2C.v
+../dv/DFFRAM_beh.v
+../rtl/IPs/QSPI_XIP_CTRL.v
+../rtl/IPs/AHBSRAM.v
+../rtl/IPs/DFFRAM.v
+../rtl/IPs/DFFRAMBB.v
++define+USE_DFFRAM_BEH=1
+../rtl/IPs/RAM_3Kx32.v
+../rtl/acc/AHB_SPM.v
+
++define+USE_DFFRAM_BEH=1
+../rtl/soc_core.v
+
+../rtl/ibex/ibex_wrapper.v
+../rtl/ibex/ibex_alu.v
+../rtl/ibex/ibex_branch_predict.v
+../rtl/ibex/ibex_compressed_decoder.v
+../rtl/ibex/ibex_controller.v
+../rtl/ibex/ibex_core.v
+../rtl/ibex/ibex_counter.v
+../rtl/ibex/ibex_cs_registers.v
+../rtl/ibex/ibex_csr.v
+../rtl/ibex/ibex_decoder.v
+../rtl/ibex/ibex_dummy_instr.v
+../rtl/ibex/ibex_ex_block.v
+../rtl/ibex/ibex_fetch_fifo.v
+../rtl/ibex/ibex_icache.v
+../rtl/ibex/ibex_id_stage.v
+../rtl/ibex/ibex_if_stage.v
+../rtl/ibex/ibex_load_store_unit.v
+../rtl/ibex/ibex_multdiv_fast.v
+../rtl/ibex/ibex_multdiv_slow.v
+../rtl/ibex/ibex_pmp.v
+../rtl/ibex/ibex_prefetch_buffer.v
+../rtl/ibex/ibex_register_file_latch.v
+../rtl/ibex/ibex_wb_stage.v
+../rtl/ibex/prim_clock_gating.v 
+../rtl/ibex/ibex_register_file_ff.v
+
+
+IBEX_SoC_TB.v
+sst26wf080b.v
+23LC512.v 
+
+

dv/files.list

@@ -0,0 +1,63 @@
+BLOCKS = $(shell find * -maxdepth 0 -type d)
+CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+OPENLANE_TAG ?= rc5
+OPENLANE_IMAGE_NAME ?= openlane:$(OPENLANE_TAG)
+OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl"
+
+all: $(BLOCKS)
+
+$(CONFIG) :
+	@echo "Missing $@. Please create a configuration for that design"
+	@exit 1
+
+$(BLOCKS) : % : ./%/config.tcl FORCE
+ifeq ($(OPENLANE_ROOT),)
+	@echo "Please export OPENLANE_ROOT"
+	@exit 1
+endif
+ifeq ($(PDK_ROOT),)
+	@echo "Please export PDK_ROOT"
+	@exit 1
+endif
+	@echo "###############################################"
+	@sleep 1
+
+	@if [ -f ./$*/interactive.tcl ]; then\
+		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(PWD)/..:/project \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
+	else\
+		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(PWD)/..:/project \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
+	fi
+
+.PHONY: openlane
+openlane:
+ifeq ($(OPENLANE_ROOT),)
+	@echo "Please export OPENLANE_ROOT"
+	@exit 1
+endif
+	git clone https://github.com/efabless/openlane.git --branch=master $(OPENLANE_ROOT) && \
+		cd $(OPENLANE_ROOT) && \
+		make openlane
+
+FORCE:
+
+clean: 
+	@echo "Use clean_all to clean everything :)"
+
+clean_all: $(CLEAN)
+
+$(CLEAN): clean-% :
+	rm -rf runs/$*
+	rm -rf ../gds/$**
+	rm -rf ../mag/$**
+	rm -rf ../lef/$**