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Run cargo clippy --fix
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jspngh committed Feb 20, 2023
1 parent 04cb499 commit a3993c9
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Showing 4 changed files with 9 additions and 9 deletions.
6 changes: 3 additions & 3 deletions build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -18,12 +18,12 @@ fn main() {
let target = target.to_string();

fs::copy(
format!("bin/trap_{}.a", target),
out_dir.join(format!("lib{}.a", name)),
format!("bin/trap_{target}.a"),
out_dir.join(format!("lib{name}.a")),
)
.unwrap();

println!("cargo:rustc-link-lib=static={}", name);
println!("cargo:rustc-link-lib=static={name}");
println!("cargo:rustc-link-search={}", out_dir.display());

// Put the linker script somewhere the linker can find it
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4 changes: 2 additions & 2 deletions src/clock.rs
Original file line number Diff line number Diff line change
Expand Up @@ -207,7 +207,7 @@ impl Strict {
let uart_clk = self
.target_uart_clk
.map(|f| f.get())
.unwrap_or(uart_clk_src as u32);
.unwrap_or(uart_clk_src);

let uart_clk_div = {
let ans = uart_clk_src / uart_clk;
Expand Down Expand Up @@ -599,7 +599,7 @@ fn aon_power_on_xtal() -> Result<(), &'static str> {
fn hbn_set_root_clk_sel_pll() {
unsafe { &*pac::HBN::ptr() }.hbn_glb.modify(|r, w| unsafe {
w.hbn_root_clk_sel()
.bits(r.hbn_root_clk_sel().bits() as u8 | 0b10u8)
.bits(r.hbn_root_clk_sel().bits() | 0b10u8)
});
}

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2 changes: 1 addition & 1 deletion src/i2c.rs
Original file line number Diff line number Diff line change
Expand Up @@ -305,7 +305,7 @@ where
}
self.i2c
.i2c_fifo_wdata
.write(|w| unsafe { w.i2c_fifo_wdata().bits(*value as u32) });
.write(|w| unsafe { w.i2c_fifo_wdata().bits(*value) });
}

while self.i2c.i2c_bus_busy.read().sts_i2c_bus_busy().bit_is_set() {
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6 changes: 3 additions & 3 deletions src/watchdog.rs
Original file line number Diff line number Diff line change
Expand Up @@ -184,7 +184,7 @@ impl ConfiguredWatchdog0 {
/// Gets the value in ticks the match register is currently set to
pub fn get_match_ticks(&self) -> u16 {
let timer = unsafe { &*pac::TIMER::ptr() };
timer.wmr.read().wmr().bits() as u16
timer.wmr.read().wmr().bits()
}

/// Get the current value of the watchdog timer in nanoseconds
Expand All @@ -197,7 +197,7 @@ impl ConfiguredWatchdog0 {
/// Get the current value in ticks of the watchdog timer
pub fn get_current_ticks(&self) -> u16 {
let timer = unsafe { &*pac::TIMER::ptr() };
timer.wvr.read().wvr().bits() as u16
timer.wvr.read().wvr().bits()
}

/// Get the current value of the watchdog timer in nanoseconds
Expand All @@ -210,7 +210,7 @@ impl ConfiguredWatchdog0 {
/// Read the TCCR register containing the CS_WDT bits that select the clock source
pub fn get_cs_wdt(&self) -> u8 {
let timer = unsafe { &*pac::TIMER::ptr() };
timer.tccr.read().cs_wdt().bits() as u8
timer.tccr.read().cs_wdt().bits()
}

/// Read the WMER register's WRIE bit to see if the WDT is in Reset or Interrupt mode.
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