File tree 5 files changed +0
-49
lines changed
5 files changed +0
-49
lines changed Original file line number Diff line number Diff line change @@ -73,7 +73,6 @@ int cpunum(void);
73
73
extern volatile uint * lapic ;
74
74
void lapiceoi (void );
75
75
void lapicinit (int );
76
- void lapic_tlbflush (uint );
77
76
void lapicstartap (uchar , uint );
78
77
void microdelay (int );
79
78
Original file line number Diff line number Diff line change @@ -47,27 +47,6 @@ lapicw(int index, int value)
47
47
lapic [ID ]; // wait for write to finish, by reading
48
48
}
49
49
50
- static uint
51
- lapicr (uint off )
52
- {
53
- return lapic [off ];
54
- }
55
-
56
- static int
57
- apic_icr_wait ()
58
- {
59
- uint i = 100000 ;
60
- while ((lapicr (ICRLO ) & BUSY ) != 0 ) {
61
- nop_pause ();
62
- i -- ;
63
- if (i == 0 ) {
64
- cprintf ("apic_icr_wait: wedged?\n" );
65
- return -1 ;
66
- }
67
- }
68
- return 0 ;
69
- }
70
-
71
50
//PAGEBREAK!
72
51
void
73
52
lapicinit (int c )
@@ -151,23 +130,6 @@ microdelay(int us)
151
130
{
152
131
}
153
132
154
-
155
- // Send IPI
156
- void
157
- lapic_ipi (int cpu , int ino )
158
- {
159
- lapicw (ICRHI , cpu << 24 );
160
- lapicw (ICRLO , FIXED | DEASSERT | ino );
161
- if (apic_icr_wait () < 0 )
162
- panic ("lapic_ipi: icr_wait failure" );
163
- }
164
-
165
- void
166
- lapic_tlbflush (uint cpu )
167
- {
168
- lapic_ipi (cpu , T_TLBFLUSH );
169
- }
170
-
171
133
#define IO_RTC 0x70
172
134
173
135
// Start additional processor running bootstrap code at addr.
Original file line number Diff line number Diff line change @@ -73,10 +73,6 @@ trap(struct trapframe *tf)
73
73
cpu -> id , tf -> cs , tf -> eip );
74
74
lapiceoi ();
75
75
break ;
76
- case T_TLBFLUSH :
77
- lapiceoi ();
78
- lcr3 (rcr3 ());
79
- break ;
80
76
81
77
//PAGEBREAK: 13
82
78
default :
Original file line number Diff line number Diff line change 25
25
// These are arbitrarily chosen, but with care not to overlap
26
26
// processor defined exceptions or interrupt vectors.
27
27
#define T_SYSCALL 64 // system call
28
- #define T_TLBFLUSH 65 // flush TLB
29
28
#define T_DEFAULT 500 // catchall
30
29
31
30
#define T_IRQ0 32 // IRQ 0 corresponds to int T_IRQ
Original file line number Diff line number Diff line change @@ -137,11 +137,6 @@ loadvm(struct proc *p)
137
137
138
138
lcr3 (PADDR (p -> pgdir )); // switch to new address space
139
139
popcli ();
140
-
141
- // Conservatively flush other processor's TLBs
142
- // XXX lazy--just 2 cpus, but xv6 doesn't need shootdown anyway.
143
- if (cpu -> id == 0 ) lapic_tlbflush (1 );
144
- else lapic_tlbflush (0 );
145
140
}
146
141
147
142
// Setup kernel part of a page table. Linear adresses map one-to-one
You can’t perform that action at this time.
0 commit comments