Parmys doc (#46)

* cleaned

* make format-py

* write arch cleaned

* yosys -> parmys

* doc update started

* ODIN_II -> odin_ii

* odin_ii refactored

Author: poname

.gitattributes

@@ -38,10 +38,10 @@ libs/EXTERNAL/**        linguist-vendored
 # External benchmarks imported into vtr_flow benchmark suite.
 vtr_flow/benchmarks/**  linguist-vendored
 vtr_flow/scripts/perl_libs/** linguist-vendored
-# External benchmarks imported into ODIN_II benchmark suite.
-ODIN_II/regression_test/benchmark/verilog/large/** linguist-vendored
-ODIN_II/regression_test/benchmark/verilog/full/** linguist-vendored
-ODIN_II/regression_test/benchmark/verilog/FIR/** linguist-vendored
+# External benchmarks imported into odin_ii benchmark suite.
+odin_ii/regression_test/benchmark/verilog/large/** linguist-vendored
+odin_ii/regression_test/benchmark/verilog/full/** linguist-vendored
+odin_ii/regression_test/benchmark/verilog/FIR/** linguist-vendored
 
 # Documentation
 doc/**                  linguist-documentation

.github/labeler.yml

@@ -17,8 +17,8 @@ blifexplorer:
  - blifexplorer/*
  - blifexplorer/**/*
 Odin:
- - ODIN_II/*
- - ODIN_II/**/*
+ - odin_ii/*
+ - odin_ii/**/*
  - odin2_helper/*
  - odin2_helper/**/*
 VPR:

.github/scripts/run-vtr.sh

@@ -9,8 +9,7 @@ export VTR_DIR=$(pwd)
 source $SCRIPT_DIR/hostsetup.sh
 
 if ! { [ $VTR_TEST == "vtr_reg_strong" ] || [ $VTR_TEST == "odin_reg_strong" ] \
-|| [ $VTR_TEST == "vtr_reg_yosys" ] \
-|| [ $VTR_TEST == "vtr_reg_yosys_parmys" ]; }; then
+|| [ $VTR_TEST == "vtr_reg_parmys" ]; }; then
 	source $SCRIPT_DIR/vtr-full-setup.sh
 fi
 

.github/workflows/test.yml

@@ -39,7 +39,6 @@ jobs:
           - {test: "vtr_reg_strong",             cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                                         extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON",                          extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
-          - {test: "vtr_reg_yosys",              cores: "16", options: "",          cmake: "",                                                             extra_pkgs: ""}
           - {test: "vtr_reg_parmys",       cores: "16", options: "",          cmake: "-DYOSYS_SV_UHDM_PLUGIN=ON",                                    extra_pkgs: ""}
           - {test: "odin_reg_strong",            cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
 

.gitignore

@@ -12,7 +12,6 @@ bin/
 CMakeCache.txt
 CMakeFiles
 build
-Yosys
 
 #
 #VTR Flow/Tasks
@@ -89,28 +88,18 @@ vgcore*
 #
 #Odin test outputs
 #
-ODIN_II/log
-ODIN_II/regression_test/run[0-9]*
-ODIN_II/temp/*
-ODIN_II/usefull_tools/**/run[0-9]*
-ODIN_II/usefull_tools/**/track_completed
+odin_ii/log
+odin_ii/regression_test/run[0-9]*
+odin_ii/temp/*
+odin_ii/usefull_tools/**/run[0-9]*
+odin_ii/usefull_tools/**/track_completed
 #
 #C/C++
 #
 *.d
 *.o
 *.a
 
-#
-#Yosys exec dir
-#
-Yosys
-
-#
-#ArchFPGA exec dir
-#
-ArchFPGA
-
 #
 #Python
 #

CMakeLists.txt

@@ -54,9 +54,8 @@ option(ODIN_TIDY "Enable building odin with clang tidy" OFF)
 option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)
 
 # Allow the user to enable building Yosys
-option(WITH_YOSYS "Enable building Yosys" ON)
+option(WITH_PARMYS "Enable Yosys as elaborator and parmys-plugin as partial mapper" ON)
 option(YOSYS_SV_UHDM_PLUGIN "Enable building and installing Yosys SystemVerilog and UHDM plugins" OFF)
-option(YOSYS_PARMYS_PLUGIN "Enable building and installing Parmys (Partial Mapper for Yosys) plugin" ON)
 
 set(VTR_VERSION_MAJOR 8)
 set(VTR_VERSION_MINOR 1)
@@ -392,7 +391,7 @@ if(${WITH_ABC})
     add_subdirectory(abc)
 endif()
 
-if(${WITH_YOSYS}) # define cmake params to compile Yosys
+if(${WITH_PARMYS}) # define cmake params to compile Yosys
     add_definitions("-D_YOSYS_")
 
     set(MAKE_PROGRAM "$(MAKE)")
@@ -410,14 +409,8 @@ endif()
 
 add_subdirectory(libs) #libs/CMakeLists.txt handles adding warnings flags to non-external libraries
 
-# check YOSYS_PARMYS_PLUGIN flag
-if(${YOSYS_PARMYS_PLUGIN})
-    if(NOT ${WITH_YOSYS})
-        message(SEND_ERROR "Using YOSYS_PARMYS_PLUGIN requires activating Yosys frontend. Please set WITH_YOSYS.")
-    endif()
-    # if (${YOSYS_PARMYS_PLUGIN})
+if(${WITH_PARMYS})
     add_subdirectory(parmys)
-    # endif ()
 endif()
 
 #Add the various tools
@@ -431,7 +424,7 @@ endif()
 add_subdirectory(utils)
 
 if(${WITH_ODIN})
-    add_subdirectory(ODIN_II)
+    add_subdirectory(odin_ii)
     # blifexplorer depends on odin
     if(${WITH_BLIFEXPLORER})
         add_subdirectory(blifexplorer)
@@ -440,9 +433,9 @@ endif()
 
 # handle cmake params to compile Yosys SystemVerilog/UHDM plugins
 if(${YOSYS_SV_UHDM_PLUGIN})
-    # avoid compiling plugins in case the Yosys frontend is not active
-    if(NOT ${WITH_YOSYS})
-        message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Yosys frontend. Please set WITH_YOSYS.")
+    # avoid compiling plugins in case the Parmys frontend is not active
+    if(NOT ${WITH_PARMYS})
+        message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Parmys frontend. Please set WITH_PARMYS.")
     endif()
 endif()
 
@@ -487,11 +480,11 @@ list(APPEND DIRS_TO_FORMAT_CPP "${CMAKE_CURRENT_SOURCE_DIR}/libs/libvtrutil")
 list(APPEND DIRS_TO_FORMAT_CPP "${CMAKE_CURRENT_SOURCE_DIR}/libs/libpugiutil")
 list(APPEND DIRS_TO_FORMAT_CPP "${CMAKE_CURRENT_SOURCE_DIR}/libs/liblog")
 list(APPEND DIRS_TO_FORMAT_CPP "${CMAKE_CURRENT_SOURCE_DIR}/libs/librtlnumber")
-list(APPEND DIRS_TO_FORMAT_CPP "${CMAKE_CURRENT_SOURCE_DIR}/ODIN_II")
+list(APPEND DIRS_TO_FORMAT_CPP "${CMAKE_CURRENT_SOURCE_DIR}/odin_ii")
 
 include(AutoClangFormat)
 
-list(APPEND DIRS_TO_FORMAT_PY "${CMAKE_CURRENT_SOURCE_DIR}/ODIN_II")
+list(APPEND DIRS_TO_FORMAT_PY "${CMAKE_CURRENT_SOURCE_DIR}/odin_ii")
 list(APPEND DIRS_TO_FORMAT_PY "${CMAKE_CURRENT_SOURCE_DIR}/ace2")
 list(APPEND DIRS_TO_FORMAT_PY "${CMAKE_CURRENT_SOURCE_DIR}/dev")
 list(APPEND DIRS_TO_FORMAT_PY "${CMAKE_CURRENT_SOURCE_DIR}/doc")

ODIN_II/odin_II

@@ -309,8 +309,7 @@ remote repository, or a PR is created, the [Test Workflow](https://github.com/ve
 will be triggered. The following tests are included in the workflow:
 * [vtr_reg_nightly_test1-3](#vtr_reg_nightly_test1-3)
 * [vtr_reg_strong](#vtr_reg_strong)
-* vtr_reg_yosys
-* vtr_reg_yosys_parmys
+* vtr_reg_parmys
 * odin_reg_strong
 
 instructions on how to gather QoR results of CI runs can be found [here](#example-extracting-qor-data-from-ci-runs).

README.developers.md

@@ -51,7 +51,7 @@ int OdinInterface::startOdin()
     /* pass arguments here to odin */
     std::vector<std::string> arguments = 
 	{
-		"../ODIN_II/odin_ii", 												//	pass the odin location relative to blifexplorer
+		"../odin_ii/odin_ii", 												//	pass the odin location relative to blifexplorer
 		"--interractive_simulation",										//	prevent odin from freeing valuable information
         "-r", "7",															//	set simulation seed
         "-sim_dir", std::string(simulation_directory + "/"),												//	set simulation directory

blifexplorer/src/odininterface.cpp

@@ -1,4 +1,4 @@
-ODIN=~/Code/vtr-repo/svn/ODIN_II/odin_II.exe
+ODIN=~/Code/vtr-repo/svn/odin_ii/odin_ii.exe
 
 EXE=verilog_preprocessor
 

dev/odin2_helper/Makefile

@@ -23,7 +23,7 @@
 paths_to_lint = [
     (repo_path, False),
     (repo_path / "dev", True),
-    (repo_path / "ODIN_II", True),
+    (repo_path / "odin_ii", True),
     (repo_path / "ace2", True),
     (repo_path / "doc", True),
     (repo_path / "vpr", True),
@@ -41,19 +41,19 @@
     repo_path / "dev/autoformat.py",
     repo_path / "dev/vpr_animate.py",
     repo_path / "dev/external_subtrees.py",
-    repo_path / "ODIN_II/usefull_tools/restore_blackboxed_latches_from_blif_file.py",
-    repo_path / "ODIN_II/regression_test/parse_result/parse_result.py",
-    repo_path / "ODIN_II/regression_test/parse_result/conf/hooks.py",
-    repo_path / "ODIN_II/regression_test/tools/parse_odin_result.py",
-    repo_path / "ODIN_II/regression_test/tools/odin_script_util.py",
-    repo_path / "ODIN_II/regression_test/tools/ODIN_CONFIG.py",
-    repo_path / "ODIN_II/regression_test/tools/synth_using_quartus.py",
-    repo_path / "ODIN_II/regression_test/tools/odin_config_maker.py",
-    repo_path / "ODIN_II/regression_test/tools/synth_using_vl2mv.py",
-    repo_path / "ODIN_II/regression_test/tools/synth_using_odin.py",
-    repo_path / "ODIN_II/regression_test/tools/asr_vector_maker.py",
-    repo_path / "ODIN_II/regression_test/tools/8_bit_arithmetic_power_output.py",
-    repo_path / "ODIN_II/regression_test/tools/8_bit_input.py",
+    repo_path / "odin_ii/usefull_tools/restore_blackboxed_latches_from_blif_file.py",
+    repo_path / "odin_ii/regression_test/parse_result/parse_result.py",
+    repo_path / "odin_ii/regression_test/parse_result/conf/hooks.py",
+    repo_path / "odin_ii/regression_test/tools/parse_odin_result.py",
+    repo_path / "odin_ii/regression_test/tools/odin_script_util.py",
+    repo_path / "odin_ii/regression_test/tools/ODIN_CONFIG.py",
+    repo_path / "odin_ii/regression_test/tools/synth_using_quartus.py",
+    repo_path / "odin_ii/regression_test/tools/odin_config_maker.py",
+    repo_path / "odin_ii/regression_test/tools/synth_using_vl2mv.py",
+    repo_path / "odin_ii/regression_test/tools/synth_using_odin.py",
+    repo_path / "odin_ii/regression_test/tools/asr_vector_maker.py",
+    repo_path / "odin_ii/regression_test/tools/8_bit_arithmetic_power_output.py",
+    repo_path / "odin_ii/regression_test/tools/8_bit_input.py",
     repo_path / "ace2/scripts/extract_clk_from_blif.py",
     repo_path / "doc/src/vtr_version.py",
     repo_path / "doc/src/conf.py",

dev/pylint_check.py

@@ -17,7 +17,7 @@
 echo "----------------------"
 echo $(git describe --always)
 
-make -j8 odin_II >& make.log
+make -j8 odin_ii >& make.log
 
 make_res=$?
 
@@ -33,7 +33,7 @@ fi
 pushd test >& /dev/null
 
 #Run the tool
-../ODIN_II/odin_II -c odin_config.xml >& odin.log
+../odin_ii/odin_ii -c odin_config.xml >& odin.log
 
 #Check for the error
 diff ref.blif LU8PEEng.odin.blif >& /dev/null

dev/test_git_bisect.sh

@@ -1,12 +1,12 @@
-PROJECT_NAME           = "Verilog to Routing - ODIN_II"
-OUTPUT_DIRECTORY       = ../_build/doxygen/ODIN_II
+PROJECT_NAME           = "Verilog to Routing - odin_ii"
+OUTPUT_DIRECTORY       = ../_build/doxygen/odin_ii
 FULL_PATH_NAMES        = NO
 OPTIMIZE_OUTPUT_FOR_C  = YES
 EXTRACT_ALL            = YES
 EXTRACT_PRIVATE        = YES
 EXTRACT_STATIC         = YES
 WARN_IF_UNDOCUMENTED   = NO
-INPUT                  = ../../ODIN_II
+INPUT                  = ../../odin_ii
 RECURSIVE              = YES
 GENERATE_HTML          = NO
 GENERATE_LATEX         = NO

doc/_doxygen/ODIN_II.dox

@@ -151,7 +151,7 @@
         "vtr": "../_build/doxygen/vtr/xml",
         "abc": "../_build/doxygen/abc/xml",
         "ace2": "../_build/doxygen/ace2/xml",
-        "ODIN_II": "../_build/doxygen/ODIN_II/xml",
+        "odin_ii": "../_build/doxygen/odin_ii/xml",
         "blifexplorer": "../_build/doxygen/blifexplorer/xml",
         "librrgraph": "../_build/doxygen/librrgraph/xml",
     }

doc/src/conf.py

@@ -64,7 +64,7 @@ Example of this configuration structure is presented below::
         "vpr"          : "../_build/doxygen/vpr/xml",
         "abc"          : "../_build/doxygen/abc/xml",
         "ace2"         : "../_build/doxygen/ace2/xml",
-        "ODIN_II"      : "../_build/doxygen/ODIN_II/xml",
+        "odin_ii"      : "../_build/doxygen/odin_ii/xml",
         "blifexplorer" : "../_build/doxygen/blifexplorer/xml",
     }
 

doc/src/dev/c_api_doc.rst

@@ -57,7 +57,7 @@ Open the Black Box
 
 At this stage, you have gotten a taste of how an FPGA architect would go about using VTR.  As a developer though, you need a much deeper understanding of how this tool works.  The purpose of this section is to have you to learn the details of the VTR CAD flow by having you manually do what the scripts do.
 
-Using the custom Verilog circuit and architecture created in the previous step, directly run Odin II on it to generate a blif netlist.  You may need to skim the ``ODIN_II/README.rst`` and the ``vtr_flow/scripts/run_vtr_flow.py``.
+Using the custom Verilog circuit and architecture created in the previous step, directly run Odin II on it to generate a blif netlist.  You may need to skim the ``odin_ii/README.rst`` and the ``vtr_flow/scripts/run_vtr_flow.py``.
 
 Using the output netlist of Odin II, run ABC to generate a technology-mapped blif file.  You may need to skim the ABC homepage (http://www.eecs.berkeley.edu/~alanmi/abc/).
 

doc/src/dev/tutorials/new_developer_tutorial.rst

@@ -35,8 +35,8 @@ For more specific documentation about VPR see :ref:`vpr`.
    vtr/index
    arch/index
    vpr/index
+   parmys/index
    odin/index
-   yosys/index
    abc/index
    tutorials/index
    utils/index

doc/src/index.rst

@@ -94,14 +94,14 @@ digraph G {
 
 Odin II uses Bison and Flex to parse a passed Verilog file and produce an Abstract Syntax Tree for each module found in the Verilog File.
 The AST is considered the "front-end" of Odin II.
-Most of the code for this can be found in verilog_bison.y, verilog_flex.l and parse_making_ast.cpp located in the ODIN_II/SRC directory.
+Most of the code for this can be found in verilog_bison.y, verilog_flex.l and parse_making_ast.cpp located in the odin_ii/SRC directory.
 
 ### AST Elaboration
 
 In this step, Odin II parses through the ASTs and elaborates specific parts like for loops, function instances, etc.
 It also will simplify the tree and rid itself of useless parts, such as an unused if statement.
 It then builds one large AST, incorporating each module.
-The code for this can mostly be found in ast_elaborate.cpp located in the ODIN_II/SRC directory.
+The code for this can mostly be found in ast_elaborate.cpp located in the odin_ii/SRC directory.
 
 > **NOTE**
 >
@@ -111,7 +111,7 @@ The code for this can mostly be found in ast_elaborate.cpp located in the ODIN_I
 
 Once again, Odin II parses through the AST assembling a Netlist.
 During the Netlist creation, pins are assigned and connected.
-The code for this can be found in netlist_create_from_ast.cpp located in the ODIN_II/SRC directory.
+The code for this can be found in netlist_create_from_ast.cpp located in the odin_ii/SRC directory.
 
 > **NOTE**
 >
@@ -132,7 +132,7 @@ The simulator of Odin II takes an Input Vector file and creates an Output Vector
 
 When making improvements to Odin II, there are some features the developer should be aware of to make their job easier.
 For instance, Odin II has a -A and -G command that prints the ASTs and Netlist viewable with GraphViz.
-These files can be found in the ODIN_II directory.
+These files can be found in the odin_ii directory.
 This is very helpful to visualize what is being created and how everything is related to each other in the Netlist and AST.
 
 Another feature to be aware of is ``make test``.

doc/src/odin/dev_guide/contributing.md

@@ -161,7 +161,7 @@ This folder is where the synthesis results and simulation results will be stored
 The task diplay name and the verilog file group should share the same title.
 
 ```bash
-└── ODIN_II
+└── odin_ii
       └── regression_test
               └── benchmark
                     ├── task
@@ -182,7 +182,7 @@ The task cmd_line_args is an example of this.
 If that is the case, each configuration file will still need its own folder, however these folders should be placed in a parent folder.
 
 ```bash
-└── ODIN_II
+└── odin_ii
       └── regression_test
               └── benchmark
                     ├── task
@@ -208,7 +208,7 @@ In the diagram below you can see the structure of the suite.
 The suite contains a configuration file that calls upon the different tasks named **task_list.conf**.
 
 ```bash
-└── ODIN_II
+└── odin_ii
       └── regression_test
               └── benchmark
                     ├── suite

doc/src/odin/dev_guide/regression_test.md

@@ -29,7 +29,7 @@ The verify_odin.sh script is designed for generating regression test results.
 
 ## Examples
 
-The following examples are being performed in the ODIN_II directory:
+The following examples are being performed in the odin_ii directory:
 
 ### Generating Results for a New Task