GitHub - KelvinChung2000/RISC-V-32IM_processor: A simple 5-stage pipeline RISC-V 32IM processor in System Verilog

KelvinChung2000 / RISC-V-32IM_processor Public

A simple 5-stage pipeline RISC-V 32IM processor in System Verilog

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
.gitignore		.gitignore
ALU.sv		ALU.sv
CSR.sv		CSR.sv
WB.sv		WB.sv
control.sv		control.sv
core.sv		core.sv
core_package.sv		core_package.sv
core_tb.cpp		core_tb.cpp
core_tb.sv		core_tb.sv
core_tb.vcd		core_tb.vcd
core_test.sh		core_test.sh
csrRegFile.sv		csrRegFile.sv
decode.sv		decode.sv
execute.sv		execute.sv
fetch.sv		fetch.sv
memory.sv		memory.sv
ram.sv		ram.sv
registerFile.sv		registerFile.sv