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Update project tt_um_urish_simon (urish/tt09-simon-game) #2

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Update project tt_um_urish_simon (urish/tt09-simon-game) #2

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c1b8f14
feat: update project tt_um_wokwi_419326042276877313 from urish/tt10-z…
TinyTapeoutBot Jan 6, 2025
a4fedd2
feat: update project tt_um_urish_simon from urish/tt09-simon-game
TinyTapeoutBot Jan 8, 2025
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14 changes: 7 additions & 7 deletions projects/tt_um_urish_simon/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"app": "Tiny Tapeout tt10 d89635e1",
"repo": "https://github.com/urish/tt10-simon-game",
"commit": "abcf605dc7b38c69764d32ab47bd92f6fa085b71",
"workflow_url": "https://github.com/urish/tt10-simon-game/actions/runs/12483024424",
"sort_id": 1734941984438,
"openlane_version": "OpenLane2 2.2.9",
"pdk_version": "open_pdks 0fe599b2afb6708d281543108caf8310912f54af"
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/urish/tt09-simon-game",
"commit": "7f5b1d54fcb7a703e43f9f7039e2e46c0905e486",
"workflow_url": "https://github.com/urish/tt09-simon-game/actions/runs/11699647032",
"sort_id": 1736325066161,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
}
10 changes: 0 additions & 10 deletions projects/tt_um_urish_simon/docs/info.md
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Expand Up @@ -14,16 +14,6 @@ The game continues until the user has made a mistake. Then a game over sound is

Check out the online simulation at https://wokwi.com/projects/408757730664700929 (including wiring diagram).

## Clock settings

The `clk_sel` input selects the clock source:
- `0`: external 50 KHz clock, provided through the `clk` input.
- `1`: internal clock, generated by the `ring_osc` module, with a frequency of ~62.5 KHz.

The internal clock is generated by a 13-stage ring oscillator, divided by 8192 to get the desired frequency. The divider value was determined by measuring the output frequency of [tt_um_urish_ringosc_cnt](https://tinytapeout.com/runs/tt05/tt_um_urish_ringosc_cnt) from Tiny Tapeout 5.

When using the internal clock, its signal is also output on the `uo_out[7]` pin for debugging purposes.

## How to test

Use a [Simon Says Pmod](https://github.com/urish/tt-simon-pmod) to test the game.
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7 changes: 2 additions & 5 deletions projects/tt_um_urish_simon/info.yaml
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Expand Up @@ -15,11 +15,8 @@ project:

# List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
source_files:
- "clock_divider_stage.v"
- "galois_lfsr.v"
- "inverter.v"
- "project.v"
- "ring_osc.v"
- "score.v"
- "simon.v"
- "sound_gen.v"
Expand All @@ -34,7 +31,7 @@ pinout:
ui[4]: "seginv"
ui[5]: ""
ui[6]: ""
ui[7]: "clk_sel"
ui[7]: ""

# Outputs
uo[0]: "led1"
Expand All @@ -44,7 +41,7 @@ pinout:
uo[4]: "speaker"
uo[5]: "dig1"
uo[6]: "dig2"
uo[7]: "clk_internal"
uo[7]: ""

# Bidirectional pins
uio[0]: "seg_a"
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260 changes: 122 additions & 138 deletions projects/tt_um_urish_simon/stats/metrics.csv
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239 changes: 61 additions & 178 deletions projects/tt_um_urish_simon/stats/synthesis-stats.txt
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@@ -1,194 +1,77 @@
70. Printing statistics.

=== clock_divider_stage ===

Number of wires: 4
Number of wire bits: 4
Number of public wires: 3
Number of public wire bits: 3
Number of ports: 3
Number of port bits: 3
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 2
sky130_fd_sc_hd__dfxtp_2 1
sky130_fd_sc_hd__inv_2 1

Chip area for module '\clock_divider_stage': 25.024000
of which used for sequential elements: 21.270400 (85.00%)

=== inverter ===

Number of wires: 2
Number of wire bits: 2
Number of public wires: 2
Number of public wire bits: 2
Number of ports: 2
Number of port bits: 2
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1
sky130_fd_sc_hd__inv_2 1

Chip area for module '\inverter': 3.753600
of which used for sequential elements: 0.000000 (0.00%)
65. Printing statistics.

=== tt_um_urish_simon ===

Number of wires: 1148
Number of wire bits: 1183
Number of public wires: 218
Number of public wire bits: 253
Number of ports: 8
Number of port bits: 43
Number of wires: 1085
Number of wire bits: 1120
Number of public wires: 190
Number of public wire bits: 225
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1164
clock_divider_stage 13
inverter 13
sky130_fd_sc_hd__a2111o_2 3
sky130_fd_sc_hd__a211o_2 12
sky130_fd_sc_hd__a211oi_2 1
sky130_fd_sc_hd__a21bo_2 5
sky130_fd_sc_hd__a21boi_2 2
sky130_fd_sc_hd__a21o_2 16
sky130_fd_sc_hd__a21oi_2 26
sky130_fd_sc_hd__a221o_2 3
sky130_fd_sc_hd__a22o_2 18
sky130_fd_sc_hd__a2bb2o_2 8
Number of cells: 1101
sky130_fd_sc_hd__a2111o_2 2
sky130_fd_sc_hd__a2111oi_2 1
sky130_fd_sc_hd__a211o_2 8
sky130_fd_sc_hd__a211oi_2 2
sky130_fd_sc_hd__a21bo_2 6
sky130_fd_sc_hd__a21boi_2 4
sky130_fd_sc_hd__a21o_2 22
sky130_fd_sc_hd__a21oi_2 29
sky130_fd_sc_hd__a221o_2 2
sky130_fd_sc_hd__a22o_2 26
sky130_fd_sc_hd__a22oi_2 1
sky130_fd_sc_hd__a2bb2o_2 5
sky130_fd_sc_hd__a311o_2 1
sky130_fd_sc_hd__a31o_2 20
sky130_fd_sc_hd__a31oi_2 6
sky130_fd_sc_hd__a32o_2 12
sky130_fd_sc_hd__a41o_2 4
sky130_fd_sc_hd__and2_2 77
sky130_fd_sc_hd__and2b_2 10
sky130_fd_sc_hd__and3_2 43
sky130_fd_sc_hd__and3b_2 9
sky130_fd_sc_hd__a311oi_2 1
sky130_fd_sc_hd__a31o_2 24
sky130_fd_sc_hd__a31oi_2 3
sky130_fd_sc_hd__a32o_2 14
sky130_fd_sc_hd__a41o_2 2
sky130_fd_sc_hd__and2_2 75
sky130_fd_sc_hd__and2b_2 11
sky130_fd_sc_hd__and3_2 37
sky130_fd_sc_hd__and3b_2 10
sky130_fd_sc_hd__and4_2 13
sky130_fd_sc_hd__and4b_2 3
sky130_fd_sc_hd__and4bb_2 2
sky130_fd_sc_hd__buf_2 2
sky130_fd_sc_hd__conb_1 9
sky130_fd_sc_hd__and4bb_2 3
sky130_fd_sc_hd__buf_2 1
sky130_fd_sc_hd__conb_1 10
sky130_fd_sc_hd__dfxtp_2 195
sky130_fd_sc_hd__inv_2 33
sky130_fd_sc_hd__mux2_1 78
sky130_fd_sc_hd__nand2_2 57
sky130_fd_sc_hd__nand2b_2 7
sky130_fd_sc_hd__nand3_2 5
sky130_fd_sc_hd__nand4_2 1
sky130_fd_sc_hd__nor2_2 64
sky130_fd_sc_hd__nor3_2 4
sky130_fd_sc_hd__nor3b_2 2
sky130_fd_sc_hd__nor4_2 3
sky130_fd_sc_hd__nor4b_2 1
sky130_fd_sc_hd__o2111a_2 2
sky130_fd_sc_hd__o2111ai_2 2
sky130_fd_sc_hd__o211a_2 62
sky130_fd_sc_hd__o211ai_2 2
sky130_fd_sc_hd__o21a_2 23
sky130_fd_sc_hd__o21ai_2 32
sky130_fd_sc_hd__o21ba_2 5
sky130_fd_sc_hd__o221a_2 12
sky130_fd_sc_hd__o22a_2 1
sky130_fd_sc_hd__o2bb2a_2 5
sky130_fd_sc_hd__o311a_2 7
sky130_fd_sc_hd__o31a_2 5
sky130_fd_sc_hd__o31ai_2 5
sky130_fd_sc_hd__o32a_2 1
sky130_fd_sc_hd__or2_2 96
sky130_fd_sc_hd__or3_2 22
sky130_fd_sc_hd__or3b_2 9
sky130_fd_sc_hd__or4_2 30
sky130_fd_sc_hd__or4b_2 4
sky130_fd_sc_hd__or4bb_2 2
sky130_fd_sc_hd__xnor2_2 35
sky130_fd_sc_hd__xor2_2 21

Area for cell type \inverter is unknown!
Area for cell type \clock_divider_stage is unknown!

Chip area for module '\tt_um_urish_simon': 12535.772800
of which used for sequential elements: 4147.728000 (33.09%)

=== design hierarchy ===

tt_um_urish_simon 1
clock_divider_stage 13
inverter 13

Number of wires: 1226
Number of wire bits: 1261
Number of public wires: 283
Number of public wire bits: 318
Number of ports: 73
Number of port bits: 108
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1177
sky130_fd_sc_hd__a2111o_2 3
sky130_fd_sc_hd__a211o_2 12
sky130_fd_sc_hd__a211oi_2 1
sky130_fd_sc_hd__a21bo_2 5
sky130_fd_sc_hd__a21boi_2 2
sky130_fd_sc_hd__a21o_2 16
sky130_fd_sc_hd__a21oi_2 26
sky130_fd_sc_hd__a221o_2 3
sky130_fd_sc_hd__a22o_2 18
sky130_fd_sc_hd__a2bb2o_2 8
sky130_fd_sc_hd__a311o_2 1
sky130_fd_sc_hd__a31o_2 20
sky130_fd_sc_hd__a31oi_2 6
sky130_fd_sc_hd__a32o_2 12
sky130_fd_sc_hd__a41o_2 4
sky130_fd_sc_hd__and2_2 77
sky130_fd_sc_hd__and2b_2 10
sky130_fd_sc_hd__and3_2 43
sky130_fd_sc_hd__and3b_2 9
sky130_fd_sc_hd__and4_2 13
sky130_fd_sc_hd__and4b_2 3
sky130_fd_sc_hd__and4bb_2 2
sky130_fd_sc_hd__buf_2 2
sky130_fd_sc_hd__conb_1 9
sky130_fd_sc_hd__dfxtp_2 208
sky130_fd_sc_hd__inv_2 59
sky130_fd_sc_hd__mux2_1 78
sky130_fd_sc_hd__nand2_2 57
sky130_fd_sc_hd__nand2b_2 7
sky130_fd_sc_hd__nand3_2 5
sky130_fd_sc_hd__nand4_2 1
sky130_fd_sc_hd__nor2_2 64
sky130_fd_sc_hd__nor3_2 4
sky130_fd_sc_hd__nor3b_2 2
sky130_fd_sc_hd__nor4_2 3
sky130_fd_sc_hd__nor4b_2 1
sky130_fd_sc_hd__o2111a_2 2
sky130_fd_sc_hd__o2111ai_2 2
sky130_fd_sc_hd__o211a_2 62
sky130_fd_sc_hd__inv_2 28
sky130_fd_sc_hd__mux2_1 75
sky130_fd_sc_hd__nand2_2 53
sky130_fd_sc_hd__nand2b_2 4
sky130_fd_sc_hd__nand3_2 4
sky130_fd_sc_hd__nand3b_2 1
sky130_fd_sc_hd__nand4_2 2
sky130_fd_sc_hd__nand4b_2 1
sky130_fd_sc_hd__nor2_2 69
sky130_fd_sc_hd__nor3_2 6
sky130_fd_sc_hd__nor3b_2 3
sky130_fd_sc_hd__nor4_2 1
sky130_fd_sc_hd__o2111a_2 3
sky130_fd_sc_hd__o211a_2 54
sky130_fd_sc_hd__o211ai_2 2
sky130_fd_sc_hd__o21a_2 23
sky130_fd_sc_hd__o21ai_2 32
sky130_fd_sc_hd__o21ba_2 5
sky130_fd_sc_hd__o221a_2 12
sky130_fd_sc_hd__o22a_2 1
sky130_fd_sc_hd__o2bb2a_2 5
sky130_fd_sc_hd__o311a_2 7
sky130_fd_sc_hd__o21ba_2 4
sky130_fd_sc_hd__o21bai_2 1
sky130_fd_sc_hd__o221a_2 15
sky130_fd_sc_hd__o22a_2 3
sky130_fd_sc_hd__o2bb2a_2 3
sky130_fd_sc_hd__o311a_2 3
sky130_fd_sc_hd__o31a_2 5
sky130_fd_sc_hd__o31ai_2 5
sky130_fd_sc_hd__o32a_2 1
sky130_fd_sc_hd__or2_2 96
sky130_fd_sc_hd__or3_2 22
sky130_fd_sc_hd__or3b_2 9
sky130_fd_sc_hd__or4_2 30
sky130_fd_sc_hd__or4b_2 4
sky130_fd_sc_hd__or4bb_2 2
sky130_fd_sc_hd__xnor2_2 35
sky130_fd_sc_hd__xor2_2 21
sky130_fd_sc_hd__o31ai_2 1
sky130_fd_sc_hd__o41a_2 1
sky130_fd_sc_hd__or2_2 86
sky130_fd_sc_hd__or3_2 16
sky130_fd_sc_hd__or3b_2 5
sky130_fd_sc_hd__or4_2 31
sky130_fd_sc_hd__or4b_2 8
sky130_fd_sc_hd__or4bb_2 3
sky130_fd_sc_hd__xnor2_2 21
sky130_fd_sc_hd__xor2_2 23

Chip area for top module '\tt_um_urish_simon': 12909.881600
of which used for sequential elements: 0.000000 (0.00%)
Chip area for module '\tt_um_urish_simon': 12165.417600

Binary file modified projects/tt_um_urish_simon/tt_um_urish_simon.gds
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