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Merge pull request #4851 from YosysHQ/nak/scopeindex_private_hdlname
handle some cases of hdlname attribute on private objects
2 parents 76d85fe + a5ba1d2 commit 398024e

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3 files changed

+28
-6
lines changed

3 files changed

+28
-6
lines changed

frontends/verific/verific.cc

+2-1
Original file line numberDiff line numberDiff line change
@@ -1464,7 +1464,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
14641464
log("Importing module %s.\n", RTLIL::id2cstr(module->name));
14651465
}
14661466
import_attributes(module->attributes, nl, nl);
1467-
module->set_string_attribute(ID::hdlname, nl->CellBaseName());
1467+
if (module->name.isPublic())
1468+
module->set_string_attribute(ID::hdlname, nl->CellBaseName());
14681469
module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
14691470
#ifdef VERIFIC_VHDL_SUPPORT
14701471
if (nl->IsFromVhdl()) {

kernel/scopeinfo.h

+12-5
Original file line numberDiff line numberDiff line change
@@ -337,12 +337,14 @@ template<typename O>
337337
std::vector<IdString> parse_hdlname(const O* object)
338338
{
339339
std::vector<IdString> path;
340-
if (!object->name.isPublic())
341-
return path;
342340
for (auto const &item : object->get_hdlname_attribute())
343341
path.push_back("\\" + item);
344-
if (path.empty())
342+
if (path.empty() && object->name.isPublic())
345343
path.push_back(object->name);
344+
if (!path.empty() && !(object->name.isPublic() || object->name.begins_with("$paramod") || object->name.begins_with("$abstract"))) {
345+
path.pop_back();
346+
path.push_back(object->name);
347+
}
346348
return path;
347349
}
348350

@@ -351,17 +353,22 @@ std::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)
351353
{
352354
std::vector<IdString> path;
353355
IdString trailing = object->name;
354-
if (object->name.isPublic()) {
356+
if (object->name.isPublic() || object->name.begins_with("$paramod") || object->name.begins_with("$abstract")) {
355357
for (auto const &item : object->get_hdlname_attribute())
356358
path.push_back("\\" + item);
357359
if (!path.empty()) {
358360
trailing = path.back();
359361
path.pop_back();
360362
}
363+
} else if (object->has_attribute(ID::hdlname)) {
364+
for (auto const &item : object->get_hdlname_attribute())
365+
path.push_back("\\" + item);
366+
if (!path.empty()) {
367+
path.pop_back();
368+
}
361369
} else {
362370
for (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), " "))
363371
path.push_back("\\" + item);
364-
365372
}
366373
return {path, trailing};
367374
}

passes/fsm/fsm_extract.cc

+14
Original file line numberDiff line numberDiff line change
@@ -377,6 +377,13 @@ static void extract_fsm(RTLIL::Wire *wire)
377377
fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
378378
fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
379379
fsm_cell->attributes = wire->attributes;
380+
if(fsm_cell->attributes.count(ID::hdlname)) {
381+
auto hdlname = fsm_cell->get_hdlname_attribute();
382+
hdlname.pop_back();
383+
fsm_cell->set_hdlname_attribute(hdlname);
384+
fsm_cell->set_string_attribute(ID(scopename), fsm_cell->get_string_attribute(ID::hdlname));
385+
fsm_cell->attributes.erase(ID::hdlname);
386+
}
380387
fsm_data.copy_to_cell(fsm_cell);
381388

382389
// rename original state wire
@@ -385,6 +392,13 @@ static void extract_fsm(RTLIL::Wire *wire)
385392
wire->attributes.erase(ID::fsm_encoding);
386393
wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
387394
module->wires_[wire->name] = wire;
395+
if(wire->attributes.count(ID::hdlname)) {
396+
auto hdlname = wire->get_hdlname_attribute();
397+
hdlname.pop_back();
398+
wire->set_hdlname_attribute(hdlname);
399+
wire->set_string_attribute(ID(scopename), wire->get_string_attribute(ID::hdlname));
400+
wire->attributes.erase(ID::hdlname);
401+
}
388402

389403
// unconnect control outputs from old drivers
390404

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