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Release version 0.46
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CHANGELOG

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List of major changes and improvements between releases
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=======================================================
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Yosys 0.45 .. Yosys 0.46-dev
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Yosys 0.45 .. Yosys 0.46
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--------------------------
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* Various
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- Added new "functional backend" infrastructure with three example
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backends (C++, SMTLIB and Rosette).
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- Added new coarse-grain buffer cell type "$buf" to RTLIL.
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- Added "-y" command line option to execute a Python script with
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libyosys available as a built-in module.
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- Added support for casting to type in Verilog frontend.
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* New commands and options
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- Added "clockgate" pass for automatic clock gating cell insertion.
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- Added "bufnorm" experimental pass to convert design into
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buffered-normalized form.
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- Added experimental "aiger2" and "xaiger2" backends, and an
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experimental "abc_new" command
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- Added "-force-detailed-loop-check" option to "check" pass.
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- Added "-unit_delay" option to "read_liberty" pass.
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* Verific support
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- Added left and right bound properties to wires when using
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specific VHDL types.
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Yosys 0.44 .. Yosys 0.45
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--------------------------

Makefile

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CXXFLAGS += -D_DEFAULT_SOURCE
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endif
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YOSYS_VER := 0.45+240
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YOSYS_VER := 0.46
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# Note: We arrange for .gitcommit to contain the (short) commit hash in
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# tarballs generated with git-archive(1) using .gitattributes. The git repo
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OBJS = kernel/version_$(GIT_REV).o
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bumpversion:
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sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile
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# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile
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ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
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docs/source/conf.py

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project = 'YosysHQ Yosys'
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author = 'YosysHQ GmbH'
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copyright ='2024 YosysHQ GmbH'
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yosys_ver = "0.45"
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yosys_ver = "0.46"
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# select HTML theme
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html_theme = 'furo'

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