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cpu::intel: Do CPU feature detection in Rust. #2439

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cpu::intel: Do CPU feature detection in Rust. #2439

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4d7aa86
cpu::intel: Rearrange imports a bit.
briansmith Mar 4, 2025
6f044e1
cpu::intel: Do CPU feature detection in Rust.
briansmith Mar 3, 2025
272682e
cpu::intel: Make SSE4.1 conditional on SSSE3, clarify SSE3 comments.
briansmith Feb 10, 2025
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1 change: 0 additions & 1 deletion Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,6 @@ repository = "https://github.com/briansmith/ring"

# Keep in sync with .github/workflows/ci.yml ("MSRV") and see the MSRV note
# in cpu/arm.rs.
# 1.66 is required on x86/x86_64 for https://github.com/rust-lang/rust/pull/101861.
rust-version = "1.66.0"

# Keep in sync with `links` below.
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3 changes: 0 additions & 3 deletions build.rs
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Expand Up @@ -66,8 +66,6 @@ const RING_SRCS: &[(&[&str], &str)] = &[

(&[ARM, X86_64, X86], "crypto/crypto.c"),

(&[X86_64, X86], "crypto/cpu_intel.c"),

(&[X86], "crypto/fipsmodule/aes/asm/aesni-x86.pl"),
(&[X86], "crypto/fipsmodule/aes/asm/ghash-x86.pl"),
(&[X86], "crypto/fipsmodule/aes/asm/vpaes-x86.pl"),
Expand Down Expand Up @@ -886,7 +884,6 @@ fn prefix_all_symbols(pp: char, prefix_prefix: &str, prefix: &str) -> String {
"LIMBS_window5_split_window",
"LIMBS_window5_unsplit_window",
"LIMB_shr",
"OPENSSL_cpuid_setup",
"aes_gcm_dec_kernel",
"aes_gcm_dec_update_vaes_avx2",
"aes_gcm_enc_kernel",
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198 changes: 0 additions & 198 deletions crypto/cpu_intel.c
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20 changes: 0 additions & 20 deletions crypto/internal.h
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Original file line number Diff line number Diff line change
Expand Up @@ -441,30 +441,10 @@ static inline void CRYPTO_store_u32_be(void *out, uint32_t v) {

// Runtime CPU feature support

#if defined(OPENSSL_X86) || defined(OPENSSL_X86_64)
// OPENSSL_ia32cap_P contains the Intel CPUID bits when running on an x86 or
// x86-64 system.
//
// Index 0:
// EDX for CPUID where EAX = 1
// Bit 30 is used to indicate an Intel CPU
// Index 1:
// ECX for CPUID where EAX = 1
// Index 2:
// EBX for CPUID where EAX = 7, ECX = 0
// Bit 14 (for removed feature MPX) is used to indicate a preference for ymm
// registers over zmm even when zmm registers are supported
// Index 3:
// ECX for CPUID where EAX = 7, ECX = 0
//
// Note: the CPUID bits are pre-adjusted for the OSXSAVE bit and the XMM, YMM,
// and AVX512 bits in XCR0, so it is not necessary to check those. (WARNING: See
// caveats in cpu_intel.c.)
#if defined(OPENSSL_X86_64)
extern uint32_t avx2_available;
extern uint32_t adx_bmi2_available;
#endif
#endif


#if defined(OPENSSL_ARM)
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