Arduino compatible Risc-V Based SOC

https://caravel-user-project.readthedocs.io

IEEE 754 floating point unit in Verilog

A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program

Open Source Single RISCV 32 bit core

SPI Master Optimized for RISC V Instruction memory Prefecth

Memory Mapped Cache

YIFIVE 32 Bit Single Core Risc V core with icache and dcache

Riscdunio with SRAM

SCR1 is a high-quality open-source RISC-V MCU core in Verilog