Stars
https://caravel-user-project.readthedocs.io
A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
SPI Master Optimized for RISC V Instruction memory Prefecth
YIFIVE 32 Bit Single Core Risc V core with icache and dcache
SCR1 is a high-quality open-source RISC-V MCU core in Verilog