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Arduino compatible Risc-V Based SOC

Tcl 144 26 Updated Jul 14, 2024
Verilog 3 4 Updated Apr 8, 2024

https://caravel-user-project.readthedocs.io

Verilog 5 1 Updated Jan 2, 2022
Verilog 5 2 Updated Mar 19, 2022

IEEE 754 floating point unit in Verilog

SystemVerilog 5 3 Updated Nov 17, 2022

A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program

Verilog 17 4 Updated Mar 22, 2023

Open Source Single RISCV 32 bit core

SystemVerilog 1 Updated Jan 13, 2022

SPI Master Optimized for RISC V Instruction memory Prefecth

SystemVerilog 4 1 Updated Jul 14, 2024

Memory Mapped Cache

SystemVerilog 1 Updated Feb 9, 2022

YIFIVE 32 Bit Single Core Risc V core with icache and dcache

SystemVerilog 2 Updated Jun 1, 2022
SystemVerilog 2 Updated Jul 14, 2024

Riscdunio with SRAM

Verilog 1 Updated Feb 25, 2022

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SystemVerilog 899 284 Updated Nov 15, 2024
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