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remove usage of dummy path #43

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remove usage of dummy path #43

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Empty file added by_id/openroad.rcx/003-success-disconnected-ios/aes_example.gds
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2 changes: 1 addition & 1 deletion by_id/openroad.rcx/003-success-disconnected-ios/config.json
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{"FP_PADFRAME_CFG": null, "DIODE_CELL": "sky130_fd_sc_hd__diode_2/DIODE", "PRIMARY_SIGNOFF_TOOL": "magic", "MAX_FANOUT_CONSTRAINT": 10, "STD_CELL_LIBRARY": "sky130_fd_sc_hd", "DECAP_CELL": ["sky130_fd_sc_hd__decap_8", "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_4", "sky130_fd_sc_hd__decap_3"], "FALLBACK_SDC_FILE": "./base_user_project_wrapper.sdc", "FILL_CELL": ["sky130_fd_sc_hd__fill*"], "SCL_POWER_PINS": ["VPWR", "VPB"], "PDN_CONNECT_MACROS_TO_GRID": true, "FP_CONTEXT_DEF": null, "VDD_NETS": ["vccd1", "vccd2", "vdda1", "vdda2"], "EXTRA_SPICE_MODELS": null, "SYNTH_EXCLUSION_CELL_LIST": "pdk_dir::libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells", "FP_IO_HLAYER": "met3", "GPIO_PADS_LEF": ["pdk_dir::libs.ref/sky130_fd_io/lef/sky130_fd_io.lef", "pdk_dir::libs.ref/sky130_fd_io/lef/sky130_ef_io.lef"], "VDD_PIN_VOLTAGE": 1.8, "CELL_PAD_EXCLUDE": ["sky130_fd_sc_hd__tap*", "sky130_fd_sc_hd__decap*", "sky130_ef_sc_hd__decap*", "sky130_fd_sc_hd__fill*"], "SYNTH_TIEHI_CELL": "sky130_fd_sc_hd__conb_1/HI", "RT_MIN_LAYER": "met1", "SYNTH_DRIVING_CELL": "sky130_fd_sc_hd__inv_2/Y", "PNR_EXCLUSION_CELL_LIST": "pdk_dir::libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells", "CELL_SPICE_MODELS": ["pdk_dir::libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice", "pdk_dir::libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice", "pdk_dir::libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice", "pdk_dir::libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice", "pdk_dir::libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"], "FP_TRACKS_INFO": "pdk_dir::libs.tech/openlane/sky130_fd_sc_hd/tracks.info", "RT_MAX_LAYER": "met4", "PNR_SDC_FILE": null, "PDN_MACRO_CONNECTIONS": ["mprj vccd2 vssd2 VPWR VGND"], "DIE_AREA": [0, 0, 2920, 3520], "GRT_LAYER_ADJUSTMENTS": [0.99, 0, 0, 0, 0, 0], "CELL_VERILOG_MODELS": ["pdk_dir::libs.ref/sky130_fd_sc_hd/verilog/primitives.v", "pdk_dir::libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"], "PDN_ENABLE_GLOBAL_CONNECTIONS": true, "LVS_INSERT_POWER_PINS": true, "CLOCK_UNCERTAINTY_CONSTRAINT": 0.25, "SCL_GROUND_PINS": ["VGND", "VNB"], "CHECK_ASSIGN_STATEMENTS": false, "TECH_LEFS": {"nom_*": "pdk_dir::libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef", "min_*": "pdk_dir::libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef", "max_*": "pdk_dir::libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef"}, "FP_IO_VLAYER": "met2", "CELL_LEFS": ["pdk_dir::libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "pdk_dir::libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef"], "IO_DELAY_CONSTRAINT": 20, "FP_ENDCAP_CELL": "sky130_fd_sc_hd__decap_3", "DPL_CELL_PADDING": 0, "FP_WELLTAP_CELL": "sky130_fd_sc_hd__tapvpwrvgnd_1", "GPL_CELL_PADDING": 0, "GPIO_PADS_LEF_CORE_SIDE": ["pdk_dir::libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef", "pdk_dir::libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef"], "CLOCK_PERIOD": 25, "SYNTH_CLK_DRIVING_CELL": null, "TIME_DERATING_CONSTRAINT": 5, "CLOCK_PORT": "wb_clk_i", "CTS_CLK_BUFFERS": ["sky130_fd_sc_hd__clkbuf_8", "sky130_fd_sc_hd__clkbuf_4", "sky130_fd_sc_hd__clkbuf_2"], "LIB": {"*_tt_025C_1v80": ["pdk_dir::libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"], "*_ss_100C_1v60": ["pdk_dir::libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"], "*_ff_n40C_1v95": ["pdk_dir::libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"]}, "CTS_MAX_CAP": 1.53169, "DATA_WIRE_RC_LAYER": "met2", "IGNORE_DISCONNECTED_MODULES": ["sky130_fd_sc_hd__conb_1"], "GND_NETS": ["vssd1", "vssd2", "vssa1", "vssa2"], "WIRE_LENGTH_THRESHOLD": null, "EXTRA_VERILOG_MODELS": ["./aes_example.v"], "CTS_ROOT_BUFFER": "sky130_fd_sc_hd__clkbuf_16", "CELL_GDS": ["pdk_dir::libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds"], "SYNTH_TIELO_CELL": "sky130_fd_sc_hd__conb_1/LO", "PLACE_SITE": "unithd", "GRT_OBS": null, "CLOCK_WIRE_RC_LAYER": "met5", "FP_CONTEXT_LEF": null, "DESIGN_NAME": "user_project_wrapper", "SYNTH_BUFFER_CELL": "sky130_fd_sc_hd__buf_2/A/X", "GPIO_PADS_VERILOG": ["pdk_dir::libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"], "DEFAULT_MAX_TRAN": null, "GND_PIN": "VGND", "MACROS": {"aes_example": {"gds": ["__openlane_dummy_path"], "lef": ["__openlane_dummy_path"], "instances": {}, "nl": [], "spef": {"min_*": ["./aes_example.min.spef"], "nom_*": ["./aes_example.nom.spef"], "max_*": ["./aes_example.max.spef"]}, "lib": {}, "spice": [], "sdf": {}, "json_h": null}}, "EXTRA_LEFS": ["./aes_example.lef"], "RCX_MERGE_VIA_WIRE_RES": true, "CELL_BB_VERILOG_MODELS": ["pdk_dir::libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox.v", "pdk_dir::libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox_pp.v"], "STA_CORNERS": ["nom_tt_025C_1v80", "nom_ss_100C_1v60", "nom_ff_n40C_1v95", "min_tt_025C_1v80", "min_ss_100C_1v60", "min_ff_n40C_1v95", "max_tt_025C_1v80", "max_ss_100C_1v60", "max_ff_n40C_1v95"], "FP_TAPCELL_DIST": 13, "EXTRA_LIBS": null, "EXTRA_GDS_FILES": null, "MAX_TRANSITION_CONSTRAINT": 0.75, "DEFAULT_CORNER": "nom_tt_025C_1v80", "CLOCK_TRANSITION_CONSTRAINT": 0.15, "GPIO_PADS_PREFIX": ["sky130_fd_io", "sky130_ef_io"], "PDK": "sky130A", "CLOCK_NET": null, "RUN_CVC": false, "VDD_PIN": "VPWR", "RCX_RULESETS": {"nom_*": "pdk_dir::libs.tech/openlane/rules.openrcx.sky130A.nom.calibre", "min_*": "pdk_dir::libs.tech/openlane/rules.openrcx.sky130A.min.calibre", "max_*": "pdk_dir::libs.tech/openlane/rules.openrcx.sky130A.max.calibre"}, "OUTPUT_CAP_LOAD": 33.442, "RCX_SDC_FILE": null, "LEC_ENABLE": false, "meta": {"openlane_version": "2.0.0b15", "step": "OpenROAD.RCX"}}
{"FP_PADFRAME_CFG": null, "DIODE_CELL": "sky130_fd_sc_hd__diode_2/DIODE", "PRIMARY_SIGNOFF_TOOL": "magic", "MAX_FANOUT_CONSTRAINT": 10, "STD_CELL_LIBRARY": "sky130_fd_sc_hd", "DECAP_CELL": ["sky130_fd_sc_hd__decap_8", "sky130_fd_sc_hd__decap_6", "sky130_fd_sc_hd__decap_4", "sky130_fd_sc_hd__decap_3"], "FALLBACK_SDC_FILE": "./base_user_project_wrapper.sdc", "FILL_CELL": ["sky130_fd_sc_hd__fill*"], "SCL_POWER_PINS": ["VPWR", "VPB"], "PDN_CONNECT_MACROS_TO_GRID": true, "FP_CONTEXT_DEF": null, "VDD_NETS": ["vccd1", "vccd2", "vdda1", "vdda2"], "EXTRA_SPICE_MODELS": null, "SYNTH_EXCLUSION_CELL_LIST": "pdk_dir::libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells", "FP_IO_HLAYER": "met3", "GPIO_PADS_LEF": ["pdk_dir::libs.ref/sky130_fd_io/lef/sky130_fd_io.lef", "pdk_dir::libs.ref/sky130_fd_io/lef/sky130_ef_io.lef"], "VDD_PIN_VOLTAGE": 1.8, "CELL_PAD_EXCLUDE": ["sky130_fd_sc_hd__tap*", "sky130_fd_sc_hd__decap*", "sky130_ef_sc_hd__decap*", "sky130_fd_sc_hd__fill*"], "SYNTH_TIEHI_CELL": "sky130_fd_sc_hd__conb_1/HI", "RT_MIN_LAYER": "met1", "SYNTH_DRIVING_CELL": "sky130_fd_sc_hd__inv_2/Y", "PNR_EXCLUSION_CELL_LIST": "pdk_dir::libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells", "CELL_SPICE_MODELS": ["pdk_dir::libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice", "pdk_dir::libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice", "pdk_dir::libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice", "pdk_dir::libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice", "pdk_dir::libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"], "FP_TRACKS_INFO": "pdk_dir::libs.tech/openlane/sky130_fd_sc_hd/tracks.info", "RT_MAX_LAYER": "met4", "PNR_SDC_FILE": null, "PDN_MACRO_CONNECTIONS": ["mprj vccd2 vssd2 VPWR VGND"], "DIE_AREA": [0, 0, 2920, 3520], "GRT_LAYER_ADJUSTMENTS": [0.99, 0, 0, 0, 0, 0], "CELL_VERILOG_MODELS": ["pdk_dir::libs.ref/sky130_fd_sc_hd/verilog/primitives.v", "pdk_dir::libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"], "PDN_ENABLE_GLOBAL_CONNECTIONS": true, "LVS_INSERT_POWER_PINS": true, "CLOCK_UNCERTAINTY_CONSTRAINT": 0.25, "SCL_GROUND_PINS": ["VGND", "VNB"], "CHECK_ASSIGN_STATEMENTS": false, "TECH_LEFS": {"nom_*": "pdk_dir::libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef", "min_*": "pdk_dir::libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef", "max_*": "pdk_dir::libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef"}, "FP_IO_VLAYER": "met2", "CELL_LEFS": ["pdk_dir::libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef", "pdk_dir::libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef"], "IO_DELAY_CONSTRAINT": 20, "FP_ENDCAP_CELL": "sky130_fd_sc_hd__decap_3", "DPL_CELL_PADDING": 0, "FP_WELLTAP_CELL": "sky130_fd_sc_hd__tapvpwrvgnd_1", "GPL_CELL_PADDING": 0, "GPIO_PADS_LEF_CORE_SIDE": ["pdk_dir::libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef", "pdk_dir::libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef"], "CLOCK_PERIOD": 25, "SYNTH_CLK_DRIVING_CELL": null, "TIME_DERATING_CONSTRAINT": 5, "CLOCK_PORT": "wb_clk_i", "CTS_CLK_BUFFERS": ["sky130_fd_sc_hd__clkbuf_8", "sky130_fd_sc_hd__clkbuf_4", "sky130_fd_sc_hd__clkbuf_2"], "LIB": {"*_tt_025C_1v80": ["pdk_dir::libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"], "*_ss_100C_1v60": ["pdk_dir::libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"], "*_ff_n40C_1v95": ["pdk_dir::libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"]}, "CTS_MAX_CAP": 1.53169, "DATA_WIRE_RC_LAYER": "met2", "IGNORE_DISCONNECTED_MODULES": ["sky130_fd_sc_hd__conb_1"], "GND_NETS": ["vssd1", "vssd2", "vssa1", "vssa2"], "WIRE_LENGTH_THRESHOLD": null, "EXTRA_VERILOG_MODELS": ["./aes_example.v"], "CTS_ROOT_BUFFER": "sky130_fd_sc_hd__clkbuf_16", "CELL_GDS": ["pdk_dir::libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds"], "SYNTH_TIELO_CELL": "sky130_fd_sc_hd__conb_1/LO", "PLACE_SITE": "unithd", "GRT_OBS": null, "CLOCK_WIRE_RC_LAYER": "met5", "FP_CONTEXT_LEF": null, "DESIGN_NAME": "user_project_wrapper", "SYNTH_BUFFER_CELL": "sky130_fd_sc_hd__buf_2/A/X", "GPIO_PADS_VERILOG": ["pdk_dir::libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"], "DEFAULT_MAX_TRAN": null, "GND_PIN": "VGND", "MACROS": {"aes_example": {"gds": ["./aes_example.gds"], "lef": ["./aes_example.lef"], "instances": {}, "nl": [], "spef": {"min_*": ["./aes_example.min.spef"], "nom_*": ["./aes_example.nom.spef"], "max_*": ["./aes_example.max.spef"]}, "lib": {}, "spice": [], "sdf": {}, "json_h": null}}, "EXTRA_LEFS": ["./aes_example.lef"], "RCX_MERGE_VIA_WIRE_RES": true, "CELL_BB_VERILOG_MODELS": ["pdk_dir::libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox.v", "pdk_dir::libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox_pp.v"], "STA_CORNERS": ["nom_tt_025C_1v80", "nom_ss_100C_1v60", "nom_ff_n40C_1v95", "min_tt_025C_1v80", "min_ss_100C_1v60", "min_ff_n40C_1v95", "max_tt_025C_1v80", "max_ss_100C_1v60", "max_ff_n40C_1v95"], "FP_TAPCELL_DIST": 13, "EXTRA_LIBS": null, "EXTRA_GDS_FILES": null, "MAX_TRANSITION_CONSTRAINT": 0.75, "DEFAULT_CORNER": "nom_tt_025C_1v80", "CLOCK_TRANSITION_CONSTRAINT": 0.15, "GPIO_PADS_PREFIX": ["sky130_fd_io", "sky130_ef_io"], "PDK": "sky130A", "CLOCK_NET": null, "RUN_CVC": false, "VDD_PIN": "VPWR", "RCX_RULESETS": {"nom_*": "pdk_dir::libs.tech/openlane/rules.openrcx.sky130A.nom.calibre", "min_*": "pdk_dir::libs.tech/openlane/rules.openrcx.sky130A.min.calibre", "max_*": "pdk_dir::libs.tech/openlane/rules.openrcx.sky130A.max.calibre"}, "OUTPUT_CAP_LOAD": 33.442, "RCX_SDC_FILE": null, "LEC_ENABLE": false, "meta": {"openlane_version": "2.0.0b15", "step": "OpenROAD.RCX"}}