x64: Lower SIMD requirement to SSE2 (bytecodealliance#6625)

All instructions in Cranelift now have lowerings for SSE2 as a baseline, even if they're not exactly the speediest things in the world. This enables lowering the baseline required for the SIMD proposal for WebAssembly to SSE2, the base features set of x86_64. Lots of tests were updated here to remove explicit `has_foo=false` annotations as they no longer have any effect. Additionally fuzzing has been updated to enable disabling `sse3` and `ssse3` which will help stress-test all previously-added lowerings.
fitzgen · Jun 22, 2023 · 0c98078 · 0c98078
1 parent 66fd3d7
commit 0c98078
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Showing 36 changed files with 47 additions and 146 deletions.
diff --git a/cranelift/codegen/meta/src/isa/x86.rs b/cranelift/codegen/meta/src/isa/x86.rs
@@ -17,15 +17,13 @@ fn define_settings(shared: &SettingGroup) -> SettingGroup {
         "has_sse3",
         "Has support for SSE3.",
         "SSE3: CPUID.01H:ECX.SSE3[bit 0]",
-        // Needed for default `enable_simd` setting.
-        true,
+        false,
     );
     let has_ssse3 = settings.add_bool(
         "has_ssse3",
         "Has support for SSSE3.",
         "SSSE3: CPUID.01H:ECX.SSSE3[bit 9]",
-        // Needed for default `enable_simd` setting.
-        true,
+        false,
     );
     let has_sse41 = settings.add_bool(
         "has_sse41",

diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs
@@ -13,7 +13,7 @@ use crate::machinst::{
     compile, CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet,
     TextSectionBuilder, VCode,
 };
-use crate::result::{CodegenError, CodegenResult};
+use crate::result::CodegenResult;
 use crate::settings::{self as shared_settings, Flags};
 use alloc::{boxed::Box, vec::Vec};
 use core::fmt;
@@ -221,39 +221,6 @@ fn isa_constructor(
     builder: &shared_settings::Builder,
 ) -> CodegenResult<OwnedTargetIsa> {
     let isa_flags = x64_settings::Flags::new(&shared_flags, builder);
-
-    // Check for compatibility between flags and ISA level
-    // requested. In particular, SIMD support requires SSSE3.
-    if !cfg!(miri) && shared_flags.enable_simd() {
-        if !isa_flags.has_sse3() || !isa_flags.has_ssse3() {
-            return Err(CodegenError::Unsupported(
-                "SIMD support requires SSE3 and SSSE3 on x86_64.".into(),
-            ));
-        }
-    }
-
     let backend = X64Backend::new_with_flags(triple, shared_flags, isa_flags);
     Ok(backend.wrapped())
 }
-
-#[cfg(test)]
-mod test {
-    use super::*;
-    use crate::settings;
-    use crate::settings::Configurable;
-
-    // Check that feature tests for SIMD work correctly.
-    #[test]
-    fn simd_required_features() {
-        let mut shared_flags_builder = settings::builder();
-        shared_flags_builder.set("enable_simd", "true").unwrap();
-        let shared_flags = settings::Flags::new(shared_flags_builder);
-        let mut isa_builder = crate::isa::lookup_by_name("x86_64").unwrap();
-        isa_builder.set("has_sse3", "false").unwrap();
-        isa_builder.set("has_ssse3", "false").unwrap();
-        assert!(matches!(
-            isa_builder.finish(shared_flags),
-            Err(CodegenError::Unsupported(_)),
-        ));
-    }
-}
diff --git a/cranelift/filetests/filetests/isa/x64/iadd-pairwise-avx.clif b/cranelift/filetests/filetests/isa/x64/iadd-pairwise-avx.clif
@@ -1,6 +1,6 @@
 test compile precise-output
 set enable_simd
-target x86_64 has_avx
+target x86_64 sse42 has_avx
 
 function %iadd_pairwise_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):

diff --git a/cranelift/filetests/filetests/isa/x64/iadd-pairwise.clif b/cranelift/filetests/filetests/isa/x64/iadd-pairwise.clif
@@ -1,6 +1,6 @@
 test compile precise-output
 set enable_simd
-target x86_64
+target x86_64 ssse3
 
 function %iadd_pairwise_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):

diff --git a/cranelift/filetests/filetests/isa/x64/simd-splat-avx2.clif b/cranelift/filetests/filetests/isa/x64/simd-splat-avx2.clif
@@ -1,6 +1,6 @@
 test compile precise-output
 set enable_simd
-target x86_64 has_avx has_avx2
+target x86_64 sse42 has_avx has_avx2
 
 function %splat_i8(i8) -> i8x16 {
 block0(v0: i8):

diff --git a/cranelift/filetests/filetests/isa/x64/sqmul_round_sat.clif b/cranelift/filetests/filetests/isa/x64/sqmul_round_sat.clif
@@ -1,5 +1,5 @@
 test compile precise-output
-target x86_64
+target x86_64 ssse3
 
 function %f1(i16x8, i16x8) -> i16x8 {
 block0(v0: i16x8, v1: i16x8):

diff --git a/cranelift/filetests/filetests/runtests/simd-band-splat.clif b/cranelift/filetests/filetests/runtests/simd-band-splat.clif
@@ -2,10 +2,11 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_sse41=false
 set enable_simd
 target x86_64
-target x86_64 skylake
+target x86_64 ssse3
+target x86_64 sse42
+target x86_64 sse42 has_avx
 target riscv64 has_v
 
 function %band_splat_const_i8x16(i8x16) -> i8x16 {

diff --git a/cranelift/filetests/filetests/runtests/simd-band.clif b/cranelift/filetests/filetests/runtests/simd-band.clif
@@ -2,10 +2,10 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_sse41=false
 set enable_simd
 target x86_64
-target x86_64 skylake
+target x86_64 sse42
+target x86_64 sse42 has_avx
 target riscv64 has_v
 
 

diff --git a/cranelift/filetests/filetests/runtests/simd-bnot.clif b/cranelift/filetests/filetests/runtests/simd-bnot.clif
@@ -2,10 +2,11 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_sse41=false
 set enable_simd
 target x86_64
-target x86_64 skylake
+target x86_64 ssse3
+target x86_64 sse42
+target x86_64 sse42 has_avx
 target riscv64 has_v
 
 

diff --git a/cranelift/filetests/filetests/runtests/simd-bor-splat.clif b/cranelift/filetests/filetests/runtests/simd-bor-splat.clif
@@ -2,10 +2,10 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_sse41=false
 set enable_simd
 target x86_64
-target x86_64 skylake
+target x86_64 sse42
+target x86_64 sse42 has_avx
 target riscv64 has_v
 
 function %bor_splat_const_i8x16(i8x16) -> i8x16 {

diff --git a/cranelift/filetests/filetests/runtests/simd-bor.clif b/cranelift/filetests/filetests/runtests/simd-bor.clif
@@ -2,10 +2,10 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_sse41=false
 set enable_simd
 target x86_64
-target x86_64 skylake
+target x86_64 sse42
+target x86_64 sse42 has_avx
 target riscv64 has_v
 
 

diff --git a/cranelift/filetests/filetests/runtests/simd-bxor-splat.clif b/cranelift/filetests/filetests/runtests/simd-bxor-splat.clif
@@ -2,10 +2,11 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_sse41=false
 set enable_simd
 target x86_64
-target x86_64 skylake
+target x86_64 sse41
+target x86_64 sse42
+target x86_64 sse42 has_avx
 target riscv64 has_v
 
 function %bxor_splat_const_i8x16(i8x16) -> i8x16 {

diff --git a/cranelift/filetests/filetests/runtests/simd-bxor.clif b/cranelift/filetests/filetests/runtests/simd-bxor.clif
@@ -2,10 +2,10 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_sse41=false
 set enable_simd
 target x86_64
-target x86_64 skylake
+target x86_64 sse42
+target x86_64 sse42 has_avx
 target riscv64 has_v
 
 

diff --git a/cranelift/filetests/filetests/runtests/simd-fadd-splat.clif b/cranelift/filetests/filetests/runtests/simd-fadd-splat.clif
@@ -1,7 +1,6 @@
 test run
 target aarch64
 target s390x
-target x86_64 ssse3 has_sse41=false
 set enable_simd
 target x86_64
 target x86_64 sse41
@@ -25,4 +24,4 @@ block0(v0: f64x2):
   v3 = fadd v0, v2
   return v3
 }
-; run: %splat_f64x2_2([0x0.0 0x1.0]) == [0x7.5 0x8.5]
+; run: %splat_f64x2_2([0x0.0 0x1.0]) == [0x7.5 0x8.5]
diff --git a/cranelift/filetests/filetests/runtests/simd-fadd.clif b/cranelift/filetests/filetests/runtests/simd-fadd.clif
@@ -1,9 +1,9 @@
 test run
 target aarch64
 target s390x
-target x86_64 ssse3 has_sse41=false
 set enable_simd
 target x86_64
+target x86_64 ssse3
 target x86_64 sse41
 target x86_64 sse42
 target x86_64 sse42 has_avx

diff --git a/cranelift/filetests/filetests/runtests/simd-fdiv.clif b/cranelift/filetests/filetests/runtests/simd-fdiv.clif
@@ -1,9 +1,9 @@
 test run
 target aarch64
 target s390x
-target x86_64 ssse3 has_sse41=false
 set enable_simd
 target x86_64
+target x86_64 ssse3
 target x86_64 sse41
 target x86_64 sse42
 target x86_64 sse42 has_avx

diff --git a/cranelift/filetests/filetests/runtests/simd-fmul.clif b/cranelift/filetests/filetests/runtests/simd-fmul.clif
@@ -1,7 +1,6 @@
 test run
 target aarch64
 target s390x
-target x86_64 ssse3 has_sse41=false
 set enable_simd
 target x86_64
 target x86_64 sse41

diff --git a/cranelift/filetests/filetests/runtests/simd-fneg.clif b/cranelift/filetests/filetests/runtests/simd-fneg.clif
@@ -1,9 +1,9 @@
 test run
 target aarch64
 target s390x
-target x86_64 ssse3 has_sse41=false
 set enable_simd
 target x86_64
+target x86_64 ssse3
 target x86_64 sse41
 target x86_64 sse42
 target x86_64 sse42 has_avx
@@ -21,4 +21,4 @@ block0(v0: f64x2):
     v1 = fneg v0
     return v1
 }
-; run: %fneg_f64x2([0x9.0 0x9.0]) == [-0x9.0 -0x9.0]
+; run: %fneg_f64x2([0x9.0 0x9.0]) == [-0x9.0 -0x9.0]
diff --git a/cranelift/filetests/filetests/runtests/simd-fsub.clif b/cranelift/filetests/filetests/runtests/simd-fsub.clif
@@ -1,7 +1,6 @@
 test run
 target aarch64
 target s390x
-target x86_64 ssse3 has_sse41=false
 set enable_simd
 target x86_64
 target x86_64 sse41

diff --git a/cranelift/filetests/filetests/runtests/simd-iabs.clif b/cranelift/filetests/filetests/runtests/simd-iabs.clif
@@ -2,9 +2,9 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_ssse3=false
 set enable_simd
 target x86_64
+target x86_64 ssse3
 target x86_64 sse41
 target x86_64 sse42
 target x86_64 sse42 has_avx

diff --git a/cranelift/filetests/filetests/runtests/simd-iadd-splat.clif b/cranelift/filetests/filetests/runtests/simd-iadd-splat.clif
@@ -2,10 +2,10 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_sse41=false
 set enable_simd
 target x86_64
-target x86_64 skylake
+target x86_64 sse42
+target x86_64 sse42 has_avx
 target riscv64 has_v
 
 function %iadd_splat_const_i8x16(i8x16) -> i8x16 {

diff --git a/cranelift/filetests/filetests/runtests/simd-iaddpairwise.clif b/cranelift/filetests/filetests/runtests/simd-iaddpairwise.clif
@@ -2,9 +2,9 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_ssse3=false
 set enable_simd
 target x86_64
+target x86_64 ssse3
 target x86_64 sse41
 target x86_64 sse42
 target x86_64 sse42 has_avx

diff --git a/cranelift/filetests/filetests/runtests/simd-insert-extract-lane.clif b/cranelift/filetests/filetests/runtests/simd-insert-extract-lane.clif
@@ -1,7 +1,6 @@
 test run
 target aarch64
 target s390x
-target x86_64 ssse3 has_sse41=false
 set enable_simd
 target x86_64
 target x86_64 sse41
@@ -20,4 +19,4 @@ block0(v5: f64):
 }
 ; run: %insertlane_preserves_upper_bits(0x0.0) == 1
 ; run: %insertlane_preserves_upper_bits(0x9.0) == 1
-; run: %insertlane_preserves_upper_bits(+Inf) == 1
+; run: %insertlane_preserves_upper_bits(+Inf) == 1
diff --git a/cranelift/filetests/filetests/runtests/simd-isub-splat.clif b/cranelift/filetests/filetests/runtests/simd-isub-splat.clif
@@ -2,10 +2,10 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_sse41=false
 set enable_simd
 target x86_64
-target x86_64 skylake
+target x86_64 sse42
+target x86_64 sse42 has_avx
 target riscv64 has_v
 
 

diff --git a/cranelift/filetests/filetests/runtests/simd-min-max.clif b/cranelift/filetests/filetests/runtests/simd-min-max.clif
@@ -1,9 +1,9 @@
 test run
 test interpret
-target x86_64 has_sse41=false
 set enable_simd
 target aarch64
 target x86_64
+target x86_64 ssse3
 target x86_64 sse41
 target x86_64 sse42
 target x86_64 sse42 has_avx

diff --git a/cranelift/filetests/filetests/runtests/simd-popcnt.clif b/cranelift/filetests/filetests/runtests/simd-popcnt.clif
@@ -2,9 +2,9 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_ssse3=false
 set enable_simd
 target x86_64
+target x86_64 ssse3
 target x86_64 sse42
 target x86_64 sse42 has_avx has_avx512vl has_avx512bitalg
 target riscv64 has_v

diff --git a/cranelift/filetests/filetests/runtests/simd-shuffle.clif b/cranelift/filetests/filetests/runtests/simd-shuffle.clif
@@ -2,9 +2,9 @@
 test run
 target aarch64
 target s390x
-target x86_64 has_ssse3=false
 set enable_simd
 target x86_64
+target x86_64 ssse3
 target x86_64 sse41
 target x86_64 sse42
 target x86_64 sse42 has_avx

diff --git a/cranelift/filetests/filetests/runtests/simd-splat.clif b/cranelift/filetests/filetests/runtests/simd-splat.clif
@@ -2,9 +2,9 @@
 test run
 target aarch64
 target s390x
-target x86_64 has_ssse3=false
 set enable_simd
 target x86_64
+target x86_64 ssse3
 target x86_64 sse41
 target x86_64 sse41 has_avx
 target x86_64 sse41 has_avx has_avx2

diff --git a/cranelift/filetests/filetests/runtests/simd-sqmulroundsat.clif b/cranelift/filetests/filetests/runtests/simd-sqmulroundsat.clif
@@ -2,9 +2,9 @@ test interpret
 test run
 target aarch64
 target s390x
-target x86_64 has_ssse3=false
 set enable_simd
 target x86_64
+target x86_64 ssse3
 target x86_64 sse41
 target x86_64 sse41 has_avx
 target riscv64 has_v

diff --git a/cranelift/filetests/filetests/runtests/simd-sqrt.clif b/cranelift/filetests/filetests/runtests/simd-sqrt.clif
@@ -1,9 +1,9 @@
 test run
 target aarch64
 target s390x
-target x86_64 ssse3 has_sse41=false
 set enable_simd
 target x86_64
+target x86_64 ssse3
 target x86_64 sse41
 target x86_64 sse42
 target x86_64 sse42 has_avx