New "perf" variant has perfCSRs.

Also increase "Slim" D$ to 4kB, I$ to 2kB. Signed-off-by: Tim Callahan <[email protected]>
litex-hub · tcal-x · Oct 5, 2020 · Oct 6, 2020 · Oct 8, 2020 · Nov 5, 2020
commit 5bb91146a62643cf606443d5366c69720906549c
diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile
@@ -1,6 +1,6 @@
 SRC := ${shell find . -type f -name \*.scala}
 
-all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv_SlimCfu.v VexRiscv_SlimCfuDebug.v VexRiscv_Fomu.v VexRiscv_FomuCfu.v
+all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv_SlimCfu.v VexRiscv_SlimCfuDebug.v VexRiscv_Fomu.v VexRiscv_FomuCfu.v VexRiscv_PerfCfu.v VexRiscv_PerfCfuDebug.v
 
 VexRiscv.v: $(SRC)
 	sbt compile "runMain vexriscv.GenCoreDefault"
@@ -38,21 +38,23 @@ VexRiscv_Full.v: $(SRC)
 VexRiscv_FullDebug.v: $(SRC)
 	sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --outputFile VexRiscv_FullDebug"
 
-# CFU versions must have module name changed because they will be wrapped
 VexRiscv_FullCfu.v: $(SRC)
 	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfu"
 
-# CFU versions must have module name changed because they will be wrapped
 VexRiscv_FullCfuDebug.v: $(SRC)
 	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfuDebug"
 
-# CFU versions must have module name changed because they will be wrapped
+VexRiscv_PerfCfu.v: $(SRC)
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_PerfCfu"
+
+VexRiscv_PerfCfuDebug.v: $(SRC)
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_PerfCfuDebug"
+
 VexRiscv_SlimCfu.v: $(SRC)
-	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 1024 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfu"
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all --cfu true --outputFile VexRiscv_SlimCfu"
 
-# CFU versions must have module name changed because they will be wrapped
 VexRiscv_SlimCfuDebug.v: $(SRC)
-	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 1024 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfuDebug"
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all -d --cfu true --outputFile VexRiscv_SlimCfuDebug"
 
 VexRiscv_Linux.v: $(SRC)
 	sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig linux-minimal --outputFile VexRiscv_Linux"

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.yaml
@@ -0,0 +1,4 @@
+iBus: !!vexriscv.BusReport
+  flushInstructions: [4111, 19, 19, 19]
+  info: !!vexriscv.CacheReport {bytePerLine: 32, size: 8192}
+  kind: cached
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.yaml
@@ -0,0 +1,5 @@
+debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0}
+iBus: !!vexriscv.BusReport
+  flushInstructions: [4111, 19, 19, 19]
+  info: !!vexriscv.CacheReport {bytePerLine: 32, size: 8192}
+  kind: cached
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml
@@ -1,4 +1,4 @@
 iBus: !!vexriscv.BusReport
   flushInstructions: [4111, 19, 19, 19]
-  info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024}
+  info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048}
   kind: cached
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml
@@ -1,5 +1,5 @@
 debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0}
 iBus: !!vexriscv.BusReport
   flushInstructions: [4111, 19, 19, 19]
-  info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024}
+  info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048}
   kind: cached