1
1
// RUN: circt-opt %s --lower-esi-to-physical -verify-diagnostics | circt-opt -verify-diagnostics | FileCheck %s
2
2
// RUN: circt-opt %s --lower-esi-ports -verify-diagnostics | circt-opt -verify-diagnostics | FileCheck --check-prefix=IFACE %s
3
- // RUN: circt-opt %s --lower-esi-to-physical --lower-esi-ports --hw-flatten-io --lower-esi-to-hw -verify-diagnostics | circt-opt -verify-diagnostics | FileCheck --check-prefix=HW %s
3
+ // RUN: circt-opt %s --lower-esi-to-physical --lower-esi-ports --hw-flatten-io --lower-esi-to-hw | FileCheck --check-prefix=HW %s
4
4
5
5
hw.module.extern @Sender (in %clk: !seq.clock , out x : !esi.channel <i4 >, out y : i8 ) attributes {esi.bundle }
6
6
hw.module.extern @ArrSender (out x : !esi.channel <!hw.array <4 xi64 >>) attributes {esi.bundle }
@@ -53,6 +53,7 @@ hw.module @test(in %clk: !seq.clock, in %rst:i1) {
53
53
// IFACE-NEXT: %[[#modport4:]] = sv.modport.get %i4ToRecv2 @source : !sv.interface<@IValidReady_i4> -> !sv.modport<@IValidReady_i4::@source>
54
54
// IFACE-NEXT: hw.instance "recv2" @Reciever(a: %[[#modport4:]]: !sv.modport<@IValidReady_i4::@source>, clk: %clk: !seq.clock) -> ()
55
55
56
+ // HW-LABEL: hw.module @test(in %clk : !seq.clock, in %rst : i1)
56
57
// After all 3 ESI lowering passes, there shouldn't be any ESI constructs!
57
58
// HW-NOT: esi
58
59
}
@@ -76,21 +77,25 @@ hw.module @InternRcvr(in %in: !esi.channel<!hw.array<4xi8>>) {}
76
77
hw.module @test2 (in %clk: !seq.clock , in %rst:i1 ) {
77
78
%ints , %c4 = hw.instance " adder" @add11 (clk : %clk: !seq.clock , ints : %ints: !esi.channel <i32 >) -> (mutatedInts : !esi.channel <i32 >, c4 : i4 )
78
79
80
+ %valid , %ready , %data = esi.snoop.vr %ints: !esi.channel <i32 >
81
+ %xact = comb.and %valid , %ready : i1
82
+
79
83
%nullBit = esi.null : !esi.channel <i4 >
80
84
hw.instance " nullRcvr" @Reciever (a : %nullBit: !esi.channel <i4 >, clk : %clk: !seq.clock ) -> ()
81
85
82
86
%nullArray = esi.null : !esi.channel <!hw.array <4 xi8 >>
83
87
hw.instance " nullInternRcvr" @InternRcvr (in : %nullArray: !esi.channel <!hw.array <4 xi8 >>) -> ()
84
88
}
85
89
// HW-LABEL: hw.module @test2(in %clk : !seq.clock, in %rst : i1) {
86
- // HW: %adder.ints_ready, %adder.mutatedInts, %adder.mutatedInts_valid, %adder.c4 = hw.instance "adder" @add11(clk: %clk: !seq.clock, ints: %adder.mutatedInts: i32, ints_valid: %adder.mutatedInts_valid: i1, mutatedInts_ready: %adder.ints_ready: i1) -> (ints_ready: i1, mutatedInts: i32, mutatedInts_valid: i1, c4: i4)
87
- // HW: [[ZERO:%.+]] = hw.bitcast %c0_i4 : (i4) -> i4
88
- // HW: sv.interface.signal.assign %i4ToNullRcvr(@IValidReady_i4::@data) = [[ZERO]] : i4
89
- // HW: [[ZM:%.+]] = sv.modport.get %{{.+}} @source : !sv.interface<@IValidReady_i4> -> !sv.modport<@IValidReady_i4::@source>
90
- // HW: hw.instance "nullRcvr" @Reciever(a: [[ZM]]: !sv.modport<@IValidReady_i4::@source>, clk: %clk: !seq.clock) -> ()
91
- // HW: %c0_i32 = hw.constant 0 : i32
92
- // HW: [[ZA:%.+]] = hw.bitcast %c0_i32 : (i32) -> !hw.array<4xi8>
93
- // HW: %nullInternRcvr.in_ready = hw.instance "nullInternRcvr" @InternRcvr(in: [[ZA]]: !hw.array<4xi8>, in_valid: %false_0: i1) -> (in_ready: i1)
90
+ // HW-NEXT: %adder.ints_ready, %adder.mutatedInts, %adder.mutatedInts_valid, %adder.c4 = hw.instance "adder" @add11(clk: %clk: !seq.clock, ints: %adder.mutatedInts: i32, ints_valid: %adder.mutatedInts_valid: i1, mutatedInts_ready: %adder.ints_ready: i1) -> (ints_ready: i1, mutatedInts: i32, mutatedInts_valid: i1, c4: i4)
91
+ // HW-NEXT: [[XACT:%.+]] = comb.and %adder.mutatedInts_valid, %adder.ints_ready : i1
92
+ // HW: [[ZERO:%.+]] = hw.bitcast %c0_i4 : (i4) -> i4
93
+ // HW: sv.interface.signal.assign %i4ToNullRcvr(@IValidReady_i4::@data) = [[ZERO]] : i4
94
+ // HW: [[ZM:%.+]] = sv.modport.get %{{.+}} @source : !sv.interface<@IValidReady_i4> -> !sv.modport<@IValidReady_i4::@source>
95
+ // HW: hw.instance "nullRcvr" @Reciever(a: [[ZM]]: !sv.modport<@IValidReady_i4::@source>, clk: %clk: !seq.clock) -> ()
96
+ // HW: %c0_i32 = hw.constant 0 : i32
97
+ // HW: [[ZA:%.+]] = hw.bitcast %c0_i32 : (i32) -> !hw.array<4xi8>
98
+ // HW: %nullInternRcvr.in_ready = hw.instance "nullInternRcvr" @InternRcvr(in: [[ZA]]: !hw.array<4xi8>, in_valid: %false_0: i1) -> (in_ready: i1)
94
99
95
100
hw.module @twoChannelArgs (in %clk: !seq.clock , in %ints: !esi.channel <i32 >, in %foo: !esi.channel <i7 >) {
96
101
%rdy = hw.constant 1 : i1
0 commit comments