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Merge pull request #424 from jordancarlin/coverage_refactor
Refactor coverage collection
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| // | ||
| // Copyright (c) 2023 Imperas Software Ltd., www.imperas.com | ||
| // Modified February 2024, [email protected] | ||
| // | ||
| // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 | ||
| // | ||
| // Licensed under the Apache License, Version 2.0 (the "License"); | ||
| // you may not use this file except in compliance with the License. | ||
| // You may obtain a copy of the License at | ||
| // | ||
| // http://www.apache.org/licenses/LICENSE-2.0 | ||
| // | ||
| // Unless required by applicable law or agreed to in writing, software | ||
| // distributed under the License is distributed on an "AS IS" BASIS, | ||
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, | ||
| // either express or implied. | ||
| // | ||
| // See the License for the specific language governing permissions and | ||
| // limitations under the License. | ||
| // | ||
| // | ||
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| `include "coverage/RISCV_coverage_pkg.svh" | ||
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| import RISCV_coverage_pkg::*; | ||
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| class coverage #( | ||
| parameter int ILEN = 32, // Instruction length in bits | ||
| parameter int XLEN = 32, // GPR length in bits | ||
| parameter int FLEN = 32, // FPR length in bits | ||
| parameter int VLEN = 256, // Vector register size in bits | ||
| parameter int NHART = 1, // Number of harts reported | ||
| parameter int RETIRE = 1 // Number of instructions that can retire during valid event | ||
| ) extends RISCV_coverage #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE); | ||
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| function new(virtual rvviTrace #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) rvvi); | ||
| super.new(rvvi); | ||
| endfunction | ||
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| function void sample(bit trap, int hart, int issue, string disass); | ||
| save_rvvi_data(trap, hart, issue, disass); | ||
| sample_extensions(hart, issue); | ||
| endfunction | ||
| endclass |
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| // | ||
| // Copyright (c) 2023 Imperas Software Ltd., www.imperas.com | ||
| // | ||
| // Copyright (c) 2023 Imperas Software Ltd., www.imperas.com | ||
| // Modified 3 Sept 2024 [email protected] | ||
| // support more EXTENSIONS | ||
| // change capitalization of sample function | ||
| // | ||
| // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 | ||
| // | ||
| // Licensed under the Apache License, Version 2.0 (the "License"); | ||
| // you may not use this file except in compliance with the License. | ||
| // You may obtain a copy of the License at | ||
| // | ||
| // http://www.apache.org/licenses/LICENSE-2.0 | ||
| // | ||
| // Unless required by applicable law or agreed to in writing, software | ||
| // distributed under the License is distributed on an "AS IS" BASIS, | ||
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, | ||
| // either express or implied. | ||
| // | ||
| // See the License for the specific language governing permissions and | ||
| // limitations under the License. | ||
| // | ||
| // | ||
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| // Modified February 2024, [email protected] | ||
| // | ||
| // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 | ||
| // | ||
| // Licensed under the Apache License, Version 2.0 (the "License"); | ||
| // you may not use this file except in compliance with the License. | ||
| // You may obtain a copy of the License at | ||
| // | ||
| // http://www.apache.org/licenses/LICENSE-2.0 | ||
| // | ||
| // Unless required by applicable law or agreed to in writing, software | ||
| // distributed under the License is distributed on an "AS IS" BASIS, | ||
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, | ||
| // either express or implied. | ||
| // | ||
| // See the License for the specific language governing permissions and | ||
| // limitations under the License. | ||
| // | ||
| // | ||
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| class RISCV_coverage | ||
| #( | ||
| parameter int ILEN = 32, // Instruction length in bits | ||
| parameter int XLEN = 32, // GPR length in bits | ||
| parameter int FLEN = 32, // FPR length in bits | ||
| parameter int VLEN = 256, // Vector register size in bits | ||
| parameter int NHART = 1, // Number of harts reported | ||
| parameter int RETIRE = 1 // Number of instructions that can retire during valid event | ||
| parameter int ILEN = 32, // Instruction length in bits | ||
| parameter int XLEN = 32, // GPR length in bits | ||
| parameter int FLEN = 32, // FPR length in bits | ||
| parameter int VLEN = 256, // Vector register size in bits | ||
| parameter int NHART = 1, // Number of harts reported | ||
| parameter int RETIRE = 1 // Number of instructions that can retire during valid event | ||
| ); | ||
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| `include "coverage/RISCV_coverage_rvvi.svh" | ||
| `include "coverage/RISCV_coverage_csr.svh" | ||
| `include "coverage/RISCV_coverage_exceptions.svh" | ||
| `include "coverage/RISCV_coverage_hazards.svh" | ||
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| // Load which extensions are supported in this configuration (from $WALLY/config/<config>/coverage.svh) | ||
| `include "coverage.svh" | ||
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| virtual rvviTrace #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) rvvi; | ||
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| function new(virtual rvviTrace #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) rvvi); | ||
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| this.rvvi = rvvi; | ||
| `cover_info("// cvw_arch_verif "); | ||
| `cover_info("// adapted from riscvISACOV Version 20231026.0"); | ||
| `cover_info("// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0"); | ||
| `cover_info("// Configuration:"); | ||
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| `ifdef COVER_BASE_RV32I | ||
| `cover_info("// BASE: RV32I"); | ||
| `endif | ||
| `ifdef COVER_BASE_RV32E | ||
| `cover_info("// BASE: RV32E"); | ||
| `endif | ||
| `ifdef COVER_BASE_RV64I | ||
| `cover_info("// BASE: RV64I"); | ||
| `endif | ||
| `ifdef COVER_BASE_RV64E | ||
| `cover_info("// BASE: RV64E"); | ||
| `endif | ||
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| `cover_info("// EXTENSIONS:"); | ||
| `include "RISCV_coverage_base_init.svh" | ||
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| endfunction | ||
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| function string get_inst_name(bit trap, int hart, int issue, string disass); // break and move this first bit out | ||
| string insbin, ins_str, ops; | ||
| int num = $sscanf (disass, "%s %s %s", insbin, ins_str, ops); | ||
| return ins_str; | ||
| endfunction | ||
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| function void sample_extensions(int hart, int issue); | ||
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| // Additional functions for coverage collection | ||
| `include "coverage/RISCV_coverage_rvvi.svh" | ||
| `include "coverage/RISCV_coverage_csr.svh" | ||
| `include "coverage/RISCV_coverage_exceptions.svh" | ||
| `include "coverage/RISCV_coverage_hazards.svh" | ||
| `include "coverage/RISCV_coverage_config.svh" | ||
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| virtual rvviTrace #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) rvvi; | ||
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| function new(virtual rvviTrace #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) rvvi); | ||
| this.rvvi = rvvi; | ||
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| // Print header information | ||
| `cover_info("\n// cvw_arch_verif "); | ||
| `cover_info("// adapted from riscvISACOV Version 20231026.0"); | ||
| `cover_info("// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0\n//"); | ||
| `cover_info("// Configuration:"); | ||
| `ifdef XLEN32 | ||
| `cover_info("// XLEN: 32"); | ||
| `endif | ||
| `ifdef XLEN64 | ||
| `cover_info("// XLEN: 64"); | ||
| `endif | ||
| `cover_info("// EXTENSIONS:"); | ||
| `include "RISCV_coverage_base_init.svh" | ||
| endfunction | ||
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| // Returns just the instruction name from the disassembly | ||
| function string get_inst_name(bit trap, int hart, int issue, string disass); | ||
| string insbin, ins_str, ops; | ||
| int num = $sscanf (disass, "%s %s %s", insbin, ins_str, ops); | ||
| return ins_str; | ||
| endfunction | ||
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| // Runs all of the sample functions created per extension from templates | ||
| function void sample_extensions(int hart, int issue); | ||
| `include "RISCV_coverage_base_sample.svh" | ||
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| endfunction | ||
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| function void sample_csrs(int hart, int issue); | ||
| endfunction | ||
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| function void sample_idv_metrics(); | ||
| endfunction | ||
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| endfunction | ||
| endclass | ||
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