OpenTimer

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3 repositories

OpenTimer
Public
A High-performance Timing Analysis Tool for VLSI Systems
parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation vlsi circuit-analysis computer-aided-design
Verilog
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Other
•145•567•52•4•Updated May 26, 2023May 26, 2023
Parser-SPEF
Public
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
eda circuits cpp17 vlsi computer-aided-design vlsi-physical-design sta spef electronic-design-automation vlsi-circuits
C++
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MIT License
•20•51•3•2•Updated Aug 7, 2022Aug 7, 2022
Parser-Verilog
Public
A Standalone Structural Verilog Parser
flex eda verilog cpp17 circuit computer-aided-design vlsi-physical-design electronic-design-automation vlsi-circuits bison-yacc
Verilog
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MIT License
•33•83•6•5•Updated Mar 31, 2022Mar 31, 2022