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    145 repositories

    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      •
      Apache License 2.0
      •811•2.7k•1.3k•365•Updated Feb 16, 2025Feb 16, 2025

    • opentitan-provisioning

      Public
      Reference OpenTitan Provisioning Infrastructure
      Go
      •
      Apache License 2.0
      •3•2•19•2•Updated Feb 15, 2025Feb 15, 2025

    • qemu

      Public
      Fork of QEMU for development of lowRISC platforms (including OpenTitan)
      C
      •
      Other
      •5.8k•5•11•2•Updated Feb 13, 2025Feb 13, 2025

    • cheriot-ibex

      Public
      cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
      SystemVerilog
      •
      Apache License 2.0
      •18•0•0•0•Updated Feb 12, 2025Feb 12, 2025

    • ot-sca

      Public
      Side-channel analysis setup for OpenTitan
      Jupyter Notebook
      •
      Apache License 2.0
      •27•29•26•9•Updated Feb 11, 2025Feb 11, 2025

    • lowrisc-nix

      Public
      lowRISC Nix Packages and Environments
      Nix
      •
      MIT License
      •5•4•1•1•Updated Feb 11, 2025Feb 11, 2025

    • misc-linters

      Public
      Some Internal Linter Scripts
      Python
      •
      Apache License 2.0
      •13•1•3•2•Updated Feb 11, 2025Feb 11, 2025

    • sonata-system

      Public
      A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
      SystemVerilog
      •
      Apache License 2.0
      •19•38•16•6•Updated Feb 10, 2025Feb 10, 2025

    • sonata-software

      Public
      Software, build flows and examples for the Sonata System
      C++
      •
      Apache License 2.0
      •10•7•2•1•Updated Feb 7, 2025Feb 7, 2025

    • hyperdebug-firmware

      Public
      Hyperdebug Firmware
      Shell
      •
      Apache License 2.0
      •3•1•0•0•Updated Jan 31, 2025Jan 31, 2025

    • ibex

      Public
      Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
      hardwarerisc-vrv32cpucore
      SystemVerilog
      •
      Apache License 2.0
      •577•1.5k•192•30•Updated Jan 24, 2025Jan 24, 2025

    • crt

      Public
      Compiler Repository Toolkit
      Starlark
      •
      Apache License 2.0
      •13•3•1•1•Updated Jan 8, 2025Jan 8, 2025

    • cheriot-sail

      Public
      Sail code model of the CHERIoT ISA
      TeX
      •
      Other
      •11•0•0•0•Updated Jan 7, 2025Jan 7, 2025

    • sail-riscv

      Public
      Sail RISC-V model
      Coq
      •
      Other
      •184•0•0•0•Updated Jan 7, 2025Jan 7, 2025

    • cheriot-rtos

      Public
      The RTOS components for the CHERIoT research platform
      C++
      •
      MIT License
      •49•1•0•0•Updated Dec 29, 2024Dec 29, 2024

    • cheriot-ibex-dv

      Public
      Standalone testbench for the CHERIoT Ibex core
      SystemVerilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Dec 17, 2024Dec 17, 2024

    • fusesoc

      Public
      Package manager and build abstraction tool for FPGA/ASIC development
      Python
      •
      BSD 2-Clause "Simplified" License
      •256•4•0•0•Updated Dec 3, 2024Dec 3, 2024

    • container-hotplug

      Public
      Hot-plug devices into a Docker container as they are plugged.
      Rust
      •4•7•2•0•Updated Dec 1, 2024Dec 1, 2024

    • lowrisc-toolchains

      Public
      UNSUPPORTED INTERNAL toolchain builds
      Shell
      •14•33•11•2•Updated Sep 23, 2024Sep 23, 2024

    • style-guides

      Public
      lowRISC Style Guides
      Creative Commons Attribution 4.0 International
      •122•388•10•1•Updated Sep 13, 2024Sep 13, 2024

    • muntjac

      Public
      64-bit multicore Linux-capable RISC-V processor
      SystemVerilog
      •
      Apache License 2.0
      •11•84•1•0•Updated Sep 12, 2024Sep 12, 2024

    • ibex-demo-system

      Public
      A demo system for Ibex including debug support and some peripherals
      C
      •
      Apache License 2.0
      •51•61•20•11•Updated Aug 23, 2024Aug 23, 2024

    • TestRIG

      Public
      Testing processors with Random Instruction Generation
      Python
      •
      Other
      •9•0•0•0•Updated Jul 31, 2024Jul 31, 2024

    • QuickCheckVEngine

      Public
      A RISC-V TestRIG Verification Engine based on QuickCheck
      Haskell
      •
      BSD 2-Clause "Simplified" License
      •10•0•0•0•Updated Jul 31, 2024Jul 31, 2024

    • riscv-llvm

      Public
      RISC-V support for LLVM projects (LLVM, Clang, ...)
      Shell
      •54•263•46•1•Updated Jul 26, 2024Jul 26, 2024

    • riscv-isa-sim

      Public
      RISC-V Functional ISA Simulator
      C
      •
      Other
      •901•14•0•1•Updated Jul 2, 2024Jul 2, 2024

    • sail

      Public
      Sail architecture definition language
      Isabelle
      •
      Other
      •124•0•0•0•Updated Jul 1, 2024Jul 1, 2024

    • lowrisc.github.io

      Public
      Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site
      HTML
      •9•12•1•0•Updated Jun 25, 2024Jun 25, 2024

    • bazel-release

      Public
      Bazel automated GitHub release process
      Shell
      •
      Apache License 2.0
      •2•1•0•1•Updated Jun 18, 2024Jun 18, 2024

    • lowrisc-web

      Public archive
      lowrisc.org web site sources
      HTML
      •
      Apache License 2.0
      •6•3•8•9•Updated Jun 6, 2024Jun 6, 2024