Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using ππ·π· of 1.2V in Cadence. Achieved DC power consumption of 18mW, phase noise of β96 dBc/Hz at offset frequency of 1 MHz, output power of 3dBm. The PLL was designed to have a tuning range of 18-23 GHz & locking was demonstrated through simulation
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Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using ππ·π· of 1.2V in Cadence 65nm CMOS process
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