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Implement emit_apply_fun_shared #12

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Implement emit_apply_fun_shared #12

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1d4c7ab
Implement part of mov_imm
maehjam Jan 14, 2025
c708cf7
WIP implement emit_apply_fun_shared
maehjam Jan 17, 2025
5f84fe3
Add test for malformed list
ziopio Jan 24, 2025
83b6c88
Add emit_ptr_val
ziopio Jan 27, 2025
5585f3c
Use r12 as TMP scratch register
ziopio Jan 27, 2025
f6b9197
Remove list TAG to expose the true address of the CONS pair
ziopio Jan 27, 2025
c2f65f7
load 2 consecutive words from memory
ziopio Jan 27, 2025
64b68b0
Store CAR in XREG0
ziopio Jan 27, 2025
fec174f
Increment ARG3, jump if < (MAX_REG -1)
ziopio Jan 27, 2025
113cb38
Store function and argument list back into the Xregisters
ziopio Jan 27, 2025
4b4dbb5
Store the error reason that is in ARG1 into the proper location
ziopio Jan 27, 2025
6daae65
Move address of apply_mfa into ARG4 and jump to raise_exception
ziopio Jan 27, 2025
b975285
Use branch to jump to LR address and return to the calling function
ziopio Jan 28, 2025
4ec3b1c
Use Branch and exchange to return to the calling function
ziopio Jan 28, 2025
db0127b
Set Mem shift to 2
ziopio Jan 28, 2025
83c8c08
Use helper functions to get CAR and CDR for better readability
ziopio Jan 29, 2025
e148e74
Initialize the x_register memory object with just the base register
ziopio Feb 4, 2025
12dc47a
Fix typo of commas, use semicolon
ziopio Feb 5, 2025
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30 changes: 21 additions & 9 deletions erts/emulator/beam/jit/arm/32/beam_asm.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -102,14 +102,10 @@ struct BeamAssembler : public BeamAssemblerCommon {
const a32::Gp ARG3 = a32::r2;
const a32::Gp ARG4 = a32::r3;

const a32::Gp VAR = a32::r6;
const a32::Gp TMP = a32::r12;

#ifdef ERTS_MSACC_EXTENDED_STATES
const arm::Mem erts_msacc_cache = getSchedulerRegRef(
offsetof(ErtsSchedulerRegisters, aux_regs.d.erts_msacc_cache));
#endif
const a32::Gp VAR = a32::r6;

static const int num_register_backed_fregs = 8;
constexpr arm::Mem getSchedulerRegRef(int offset) const {
ASSERT((offset & (sizeof(Eterm) - 1)) == 0);
return arm::Mem(scheduler_registers, offset);
Expand Down Expand Up @@ -273,10 +269,14 @@ struct BeamAssembler : public BeamAssemblerCommon {
}

a32::Gp emit_ptr_val(a32::Gp Dst, a32::Gp Src) {
a32::Gp r;
#if !defined(TAG_LITERAL_PTR)
return Src;
#else
// TODO
// TAG_LITERAL_PTR is undefined in ARCH_32 and may be not needed
ASSERT(false);
return r;
return Dst;
#endif
}

void emit_untag_ptr(a32::Gp Dst, a32::Gp Src) {
Expand Down Expand Up @@ -326,7 +326,19 @@ struct BeamAssembler : public BeamAssemblerCommon {
template<typename T>
void mov_imm(a32::Gp to, T value) {
// TODO
ASSERT(false);
// implement this for emit_apply_fun_shared
static_assert(std::is_integral<T>::value || std::is_pointer<T>::value);
if (value) {
ASSERT(false);
a.mov(to, imm(value));
} else {
// arm64 uses the xzr register (ZERO) here and
// x86 uses some x86 specific instruction sequence
// to set the register to zero.
// We need to understand how one sets a register to zero in
// arm32
a.mov(to, 0);
}
}

void mov_imm(a32::Gp to, std::nullptr_t value) {
Expand Down
71 changes: 69 additions & 2 deletions erts/emulator/beam/jit/arm/32/instr_fun.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -81,8 +81,75 @@ void BeamModuleAssembler::emit_i_make_fun3(const ArgLambda &Lambda,
}

void BeamGlobalAssembler::emit_apply_fun_shared() {
// TODO
ASSERT(false);
// TODO this is the first called emitter
Label finished = a.newLabel();

/* Put the arity and fun into the right registers for `call_fun`, and stash
* the argument list in ARG2 for the error path. We'll bump the arity as
* we go through the argument list. */
mov_imm(ARG3, 0);
a.ldr(ARG4, getXRef(0));
a.ldr(ARG2, getXRef(1));
{
Label unpack_next = a.newLabel(), malformed_list = a.newLabel(),
raise_error = a.newLabel();

auto x_register = arm::Mem(scheduler_registers);

ASSERT(x_register.shift() == 0);
x_register.setIndex(ARG3);
x_register.setShift(2);

a.mov(ARG1, ARG2);
a.bind(unpack_next);
{
a.cmp(ARG1, imm(NIL));
a.b_eq(finished);

ERTS_CT_ASSERT(_TAG_PRIMARY_MASK - TAG_PRIMARY_LIST == (1 << 1));
a.tst(ARG1, imm(1));
a.b_ne(malformed_list);

emit_ptr_val(ARG1, ARG1);
a.ldr(TMP, getCARRef(ARG1));
a.ldr(ARG1, getCDRRef(ARG1));
a.str(TMP, x_register);
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this fails emission....

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Passing a Mem object is fine and emission succeeds wiht getXRef(0) but it fails if the operand has been setup with setIndex and setShift.

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According to ChatGPT we need another register to use STR:

    ; Load the address of 'var' into r1 (or any free register).
    LDR   r1, =var      ; r1 now has the address of var

    ; Store r0 (32 bits) into [r1].
    STR   r0, [r1]

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In this code the register used as base register is inside x_register memory object operator. It is defined at creation using one of the available constructors of class arm::Mem

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I don't get the steps anyway. The return of getCARRef is type arm:mem and x_register is type arm:mem. Can we just directly put the return of getCARRef in x_register?

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This fails because getXReg adds an offset and we want to use a scale and an index register. We cannot use everything.
A correct initialization would be auto x_register = arm::Mem(scheduler_registers);


/* We bail at MAX_REG-1 rather than MAX_REG as the highest register
* is reserved for the loader. */
a.add(ARG3, ARG3, imm(1));
a.cmp(ARG3, imm(MAX_REG - 1));
a.b_lo(unpack_next);
}

a.mov(ARG1, imm(SYSTEM_LIMIT));
a.b(raise_error);

a.bind(malformed_list);
a.mov(ARG1, imm(BADARG));

a.bind(raise_error);
{
static const ErtsCodeMFA apply_mfa = {am_erlang, am_apply, 2};

a.str(ARG4, getXRef(0));
a.str(ARG2, getXRef(1));

a.str(ARG1, arm::Mem(c_p, offsetof(Process, freason)));
mov_imm(ARG4, &apply_mfa);
a.b(labels[raise_exception]);
}
}

a.bind(finished);
{
/* Make the lower 16 bits of ARG3 equal those of the header word of all
* funs with the same arity. */
a.lsl(ARG3, ARG3, imm(FUN_HEADER_ARITY_OFFS));
a.add(ARG3, ARG3, imm(FUN_SUBTAG));

a.bx(a32::lr);
}
}

void BeamModuleAssembler::emit_i_apply_fun() {
Expand Down