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CPU Verification Engineer | SiFive Inc
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Dadda-Multiplier-using-CSA
Dadda-Multiplier-using-CSA PublicDadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
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RISC-V-32I-based-core-with-Advanced-Extensible-Interface
RISC-V-32I-based-core-with-Advanced-Extensible-Interface Public5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
Verilog 8
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sobel-edge-detector
sobel-edge-detector PublicSobel is first order or gradient based edge operator for images and it is implemented using verilog.
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Speaker-recognition
Speaker-recognition PublicAn automatic speaker recognition system built from digital signal processing tools, Vector Quantization and LBG algorithm
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Multi-operations-toolbox-with-baugh-wooley-multiplier
Multi-operations-toolbox-with-baugh-wooley-multiplier PublicGiven A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier
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7 contributions in the last year
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