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UC Berkeley Architecture Research

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  1. chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala 1.8k 691

  2. chiseltest Public archive

    The batteries-included testing and formal verification library for Chisel-based RTL designs.

    Scala 231 76

  3. dsptools Public

    A Library of Chisel3 Tools for Digital Signal Processing

    Scala 234 39

  4. chisel-tutorial Public

    chisel tutorial exercises and answers

    Scala 716 198

Repositories

Showing 10 of 194 repositories
  • chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala 1,803 BSD-3-Clause 691 147 (3 issues need help) 33 Updated Apr 1, 2025
  • XNNPACK Public Forked from google/XNNPACK

    High-efficiency floating-point neural network inference operators for mobile, server, and Web

    C 0 426 0 0 Updated Apr 1, 2025
  • IsaacLab Public Forked from isaac-sim/IsaacLab

    Unified framework for robot learning built on NVIDIA Isaac Sim

    Python 0 1,521 0 0 Updated Apr 1, 2025
  • MaDa Public

    A mill based FPGA shell.

    Verilog 2 MIT 0 0 1 Updated Apr 1, 2025
  • executorch Public Forked from pytorch/executorch

    On-device AI across mobile, embedded and edge for PyTorch

    C++ 0 505 0 0 Updated Apr 1, 2025
  • saturn-vectors Public

    Chisel RISC-V Vector 1.0 Implementation

    Assembly 89 BSD-3-Clause 9 2 0 Updated Mar 30, 2025
  • shuttle Public

    A Rocket-based RISC-V superscalar in-order core

    Scala 31 5 1 0 Updated Mar 30, 2025
  • ara-wrapper Public
    Scala 2 0 0 0 Updated Mar 30, 2025
  • sp24-Baremetal-IDE Public Forked from ucb-bar/Baremetal-IDE

    A submodule of Chipyard https://github.com/ucb-bar/chipyard

    HTML 1 11 0 1 Updated Mar 28, 2025
  • hammer Public

    Hammer: Highly Agile Masks Made Effortlessly from RTL

    Python 272 BSD-3-Clause 60 205 (5 issues need help) 17 Updated Mar 27, 2025
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