Rename some (wrong named) macro in samv71q-pinctrl.h for AFEC0 pins

[zebo9x]

The pin macro for SAM V71 Q relative to PE5 use as AFEC0 AD3 is now named PE5X_AFE0_AD3. Previously it was named as if it is relative to AFEC1 AD3 (PE5X_AFE1_AD3). A check can be made by reading the pinout table of ATSAMV71 for 144 pinout (datasheet: https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/DataSheets/SAM-E70-S70-V70-V71-Family-Data-Sheet-DS60001527.pdf) (start fo the table: page 28; relevant table section: page 33, LQFP pin 28).

[zebo9x]

note that I didn't change the comment above the macro definition

[zebo9x]

I think the changes for AD pins for AFEC0 / AFEC1 are done.

I have tested on the EVB of ATSAMV71Q21B (the sam_v71_xult board) by using a custom board folder with inside the devicetree (common and pinctrl).
In the code I'm using the property
/zephyr,user/io-channels = <&afec0, 0>, ...;
and the propery of pinctrl/.../pinmux is a list of all the pins.

[nandojve]

Hi @zebo9x ,

Yes, you are right. There is a typo in the pinconfig file:

hal_atmel/pinconfigs/sam-s70-e70-v7x.yml

Lines 802 to 815 in 56d60eb

	pe4:
	pincodes: [q]
	periph:
	- [a, ebi, d12, [j, n]]
	- [b, tc3, tiob10]
	extra:
	- [x, afe1, ad4]
	pe5:
	pincodes: [q]
	periph:
	- [a, ebi, d13, [j, n]]
	- [b, tc3, tclk10]
	extra:
	- [x, afe1, ad3]

You should fix in there and regenerate the files. There are documentation in the repo that explains how it works.
Make sure you follow the code guidelines when you write the commit, you should respect brief and comments max columns.

[nandojve]

Hi @zebo9x,

Is there any news from your side?