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Merge pull request #308 from yrabbit/sync-with-nextpnr-w
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Remove examples that use gowin-nextpnr.
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yrabbit authored Feb 14, 2025
2 parents d4f8dec + bfdcdf1 commit cbbcce3
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Showing 294 changed files with 894 additions and 5,475 deletions.
9 changes: 1 addition & 8 deletions .github/workflows/chipdb.yml
Original file line number Diff line number Diff line change
Expand Up @@ -309,13 +309,11 @@ jobs:
git submodule update --init --recursive
mkdir -p build
cd build
cmake .. -DBUILD_PYTHON=OFF -DARCH="gowin;himbaechel" -DHIMBAECHEL_UARCH=gowin -DHIMBAECHEL_GOWIN_DEVICES="all" -DPython3_EXECUTABLE=${{ steps.pysetup.outputs.python-path }}
cmake .. -DBUILD_PYTHON=OFF -DARCH="himbaechel" -DHIMBAECHEL_UARCH=gowin -DHIMBAECHEL_GOWIN_DEVICES="all" -DPython3_EXECUTABLE=${{ steps.pysetup.outputs.python-path }}
make -j$(nproc)
sudo make install
cd ../../examples
make -j$(nproc) all
cd himbaechel
make -j$(nproc) -f Makefile.himbaechel all
- name: Archive artifact
uses: actions/upload-artifact@v4
with:
Expand All @@ -328,8 +326,3 @@ jobs:
for f in *-unpacked.v; do
yosys -p "read_verilog $f; read_verilog -lib +/gowin/cells_sim.v; clean -purge; select -assert-any t:DFF*; select -assert-any t:*BUF;";
done
cd himbaechel
make -j$(nproc) -f Makefile.himbaechel unpacked
for f in *-unpacked.v; do
yosys -p "read_verilog $f; read_verilog -lib +/gowin/cells_sim.v; clean -purge; select -assert-any t:DFF*; select -assert-any t:*BUF;";
done
7 changes: 2 additions & 5 deletions Makefile
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Expand Up @@ -11,13 +11,10 @@ all: apycula/GW1N-1.pickle apycula/GW1N-9.pickle apycula/GW1N-4.pickle \
%_stage1.pickle: apycula/tiled_fuzzer.py
python3 -m apycula.tiled_fuzzer $*

%_stage2.pickle: apycula/clock_fuzzer.py %_stage1.pickle
python3 -m apycula.clock_fuzzer $*

%_stage3.pickle: apycula/find_sdram_pins.py %_stage2.pickle
%_stage2.pickle: apycula/find_sdram_pins.py %_stage1.pickle
python3 -m apycula.find_sdram_pins $*

apycula/%.pickle: %_stage3.pickle
apycula/%.pickle: %_stage2.pickle
gzip -c $< > $@

clean:
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