QuickLogic DSPv2 support #4932
Draft
QuickLogic DSPv2 support #4932
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
…n model unchanged
Add support for cell type dispatching of the new DSP block; adjust the definition of MULT and MULTACC variants to support those instances starting a cascading chain.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
What are the reasons/motivation for this change?
Add support for v2 DSP block per a simulation model provided by QuickLogic. Support mapping basic multiplication operation, multiply-accumulate pattern, input and output register packing, sum-of-products cascading.
Explain how this is achieved.
Build a flow analogous to v1 DSP support, borrow pattern matcher bits from Xilinx flow.
If applicable, please suggest to reviewers how they can test the change.
Tests attached
Before we merge: